Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQD7N20LTM, MOSFET

FQD7N20L / FQU7N20L

200V LOGIC N-Channel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology is especially tailored to minimize

on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation modes. These devices are

well suited for high efficiency switching DC/DC converters,

switch mode power supplies, and motor control.

Features

• 5.5A, 200V, R

DS(on)

= 0.75Ω @V

= 10 V

• Low gate charge ( typical 6.8 nC)

• Low Crss ( typical 8.5 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

• Low level gate drive requirement allowing direct

operation from logic drivers

I-PAK

FQU Series

D-PAK

FQD Series

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter FQD7N20L / FQU7N20L Units

DSS

Drain-Source Voltage 200 V

Drain Current

- Continuous (T

= 25°C)

5.5 A

- Continuous (T

= 100°C)

3.48 A

Drain Current - Pulsed

(Note 1)

22 A

GSS

Gate-Source Voltage ± 20 V

Single Pulsed Avalanche Energy

(Note 2)

73 mJ

Avalanche Current

(Note 1)

5.5 A

Repetitive Avalanche Energy

(Note 1)

4.5 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

5.5 V/ns

Power Dissipation (T

= 25°C) *

2.5 W

Power Dissipation (T

= 25°C)

45 W

- Derate above 25°C 0.36 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8” from case for 5 seconds

300 °C

Symbol Parameter Typ Max Units

θJC

Thermal Resistance, Junction-to-Case -- 2.78 °C/W

θJA

Thermal Resistance, Junction-to-Ambient * -- 50 °C/W

θJA

Thermal Resistance, Junction-to-Ambient -- 110 °C/W

* When mounted on the minimum pad size recommended (PCB Mount)

October 2008

QFET

• RoHS Compliant

Summary of content (9 pages)

PAGE 1
QFET ® FQD7N20L / FQU7N20L 200V LOGIC N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation modes.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 200 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.
PAGE 3
FQD7N20L / FQU7N20L Typical Characteristics ID, Drain Current [A] Bottom : VGS 10 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 1 10 ID, Drain Current [A] Top : 1 10 0 10 150℃ 0 10 25℃ ※ Notes : 1. 250μs Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 30V 2. 250μs Pulse Test -55℃ -1 -1 10 -1 0 10 10 1 10 0 10 2 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2.
PAGE 4
FQD7N20L / FQU7N20L Typical Characteristics (Continued) 1.2 3.0 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 3.25 A 0.5 0.0 -100 200 -50 0 o 100 150 200 o TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQD7N20L / FQU7N20L Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 5V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 5V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2008 Fairchild Semiconductor International ID (t) VDS (t) VDD tp T
PAGE 6
FQD7N20L / FQU7N20L Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2008 Fairchild Semiconductor International Rev.
PAGE 7
FQD7N20L / FQU7N20L Mechanical Dimensions D - PAK Dimensions in Millimeters ©2008 Fairchild Semiconductor International Rev.
PAGE 8
FQD7N20L / FQU7N20L Mechanical Dimensions I - PAK Dimensions in Millimeters ©2008 Fairchild Semiconductor International Rev.
PAGE 9
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