Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQL40N50, MOSFET

November 2013

Thermal Characteristics

FQL40N50

N-Channel QFET

MOSFET

500 V, 40 A, 110 mΩ

Description

FQL40N50 Rev. C1

www.fairchildsemi.com

FQL40N50 — N-Channel QFET

MOSFET

This N-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor’s proprietary planar

stripe and DMOS technology. This advanced MOSFET

technology has been especially tailored to reduce on-state

resistance, and to provide superior switching performance

and high avalanche energy strength. These devices are

suitable for switched mode power supplies, active power

factor correction (PFC), and electronic lamp ballasts.

Features

•

40 A, 500 V, R

DS(on)

= 110 mΩ (Max.) @ V

= 10 V,

= 20 A

•

Low Gate Charge (Typ. 155 nC)

•

Low Crss (Typ. 95 pF)

• 100% Avalanche Tested

Absolute Maximum Ratings T

= 25°C unless otherwise noted.

TO-264

Symbol Parameter FQL40N50

Unit

DSS

Drain-Source Voltage 500 V

Drain Current

- Continuous (T

= 25°C)

40 A

- Continuous (T

= 100°C)

25 A

Drain Current - Pulsed

(Note 1)

160 A

GSS

Gate-Source Voltage ± 30 V

Single Pulsed Avalanche Energy

(Note 2)

1780 mJ

Avalanche Current

(Note 1)

40 A

Repetitive Avalanche Energy

(Note 1)

46 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

4.5 V/ns

Power Dissipation (T

= 25°C)

460 W

- Derate above 25°C 3.7 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering,

1/8" from cas

e for 5 seconds.

300 °C

 

FQL40N50





Thermal Resistance, Junction-to-Case, Max.

0.27

6?



Thermal Resistance, Junction-to-Ambient, Max.

6?

Summary of content (8 pages)

PAGE 1
FQL40N50 N-Channel QFET® MOSFET 500 V, 40 A, 110 mΩ Description Features This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Part Number Electrical Characteristics Symbol Package TO-264 Top Mark FQL40N50 FQL40N50 Packing Method Tube Reel Size Tape Width N/A N/A Quantity 25 units TC = 25°C unless otherwise noted. Parameter Test Conditions Min. Typ. Max. Unit 500 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.
PAGE 3
VGS 15 V 10 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom : 5.5 V ID , Drain Current [A] ID , Drain Current [A] 2 10 Top : 2 10 1 10 150℃ 1 10 25℃ -55℃ 0 10 ※ Notes : 1. VDS = 50V 2. 250μ s Pulse Test ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ 0 -1 10 -1 10 0 10 1 10 2 10 4 6 8 10 VGS , Gate-Source Voltage [V] VDS , Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.4 2 0.
PAGE 4
(Continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 20 A 0.5 150 0.0 -100 200 -50 0 50 100 150 o o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
200nF 12V FQL40N50 — N-Channel QFET® MOSFET VGS Same Type as DUT 50KΩ Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 13. Resistive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp Time tp Figure 14.
PAGE 6
+ VDS _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2000 Fairchild Semiconductor Corporation FQL40N50 Rev. C1 6 www.
PAGE 7
FQL40N50 — N-Channel QFET® MOSFET Mechanical Dimensions Figure 16. TO264, Molded, 3-Lead, Jedec Variation AA Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.