Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQP17P10, MOSFET

FQP17P10 P-Channel QFET

MOSFET

March 2013

FQP17P10 Rev.C0

FQP17P10

P-Channel QFET

MOSFET

- 100 V, - 16.5 A, 190 m

Description

This P-Channel enhancement mode power MOSFET is

produced using Fairchild Semiconductor

’s proprietary

planar stripe and DMOS technology. This advanced

MOSFET technology has been especially tailored to reduce

on-state resistance, and to provide superior switching

performance and high avalanche energy strength. These

devices are suitable for switched mode power supplies,

audio amplifier, DC motor control, and variable switching

power applications.

Features

• -16.5 A, -100 V, R

DS(on)

= 190 m (Max.) @V

= -10 V,

= - 8.25 A

• Low Gate Charge (Typ. 30 nC)

• Low Crss (Typ. 100 pF)

• 100% Avalanche Tested

• 175C Maximum Junction Temperature Rating

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter FQP17P10 Unit

DSS

Drain-Source Voltage -100 V

Drain Current

- Continuous (T

= 25°C)

-16.5 A

- Continuous (T

= 100°C)

-11.7 A

Drain Current - Pulsed

(Note 1)

-66 A

GSS

Gate-Source Voltage  30 V

Single Pulsed Avalanche Energy

(Note 2)

580 mJ

Avalanche Current

(Note 1)

-16.5 A

Repetitive Avalanche Energy

(Note 1)

10 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

-6.0 V/ns

Power Dissipation (T

= 25°C)

100 W

- Derate above 25°C 0.67 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +175 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

Symbol Parameter FQP17P10 Unit

JC

Thermal Resistance, Junction-to-Case, Max. 1.5 °C/W

CS

Thermal Resistance, Case-to-Sink, Typ. 0.5 °C/W

JA

Thermal Resistance, Junction-to-Ambient, Max. 62.5 °C/W

TO-220

Summary of content (8 pages)

PAGE 1
FQP17P10 P-Channel QFET® MOSFET - 100 V, - 16.5 A, 190 m Description Features This P-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor®’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions  Off Characteristics Min Typ Max Unit -100 -- -- V -- V/°C BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 A BVDSS / TJ Breakdown Voltage Temperature Coefficient ID = -250 A, Referenced to 25°C -- -0.
PAGE 3
VGS -15.0 V -10.0 V -8.0 V -7.0 V -6.5 V -5.5 V -5.0 V Bottom : -4.5 V 1 10 -ID , Drain Current [A] -ID, Drain Current [A] Top : 0 10 1 10 175℃ 0 10 25℃ -55℃ ※ Notes : 1. VDS = -40V 2. 250μ s Pulse Test ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ -1 10 -1 10 -1 0 10 2 1 10 10 4 6 8 10 -VGS , Gate-Source Voltage [V] -VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics VGS = - 10V 0.5 0.4 VGS = - 20V 0.3 0.2 0.1 0.
PAGE 4
(Continued) 2.5 RDS(ON), (Normalized) Drain-Source On-Resistance -BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = -250 μA 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = -10 V 2. ID = -8.25 A 0.5 0.0 -100 200 -50 o 0 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQP17P10 P-Channel QFET® MOSFET Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ 200nF 12V Qg -10V 300nF VDS VGS Qgs Qgd DUT -3mA Charge Resistive Switching Test Circuit & Waveforms VDS RG RL t on VDD VGS td(on) VGS t off tr td(off) tf 10% DUT -10V VDS 90% Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS tp ID RG VDD DUT -10V VDD Time VDS (t) ID (t) IAS BVDSS tp Dimensions in Millime
PAGE 6
FQP17P10 P-Channel QFET® MOSFET Peak Diode Recovery dv/dt Test Circuit & Waveforms + VDS DUT _ I SD L Driver RG VGS VGS ( Driver ) Compliment of DUT (N-Channel) VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V Body Diode Reverse Current I SD ( DUT ) IRM di/dt IFM , Body Diode Forward Current VDS ( DUT ) VSD Body Diode Forward Voltage Drop VDD Body Diode Recovery dv/dt ©2002 Fairchild Semiconductor Corporatio
PAGE 7
FQP17P10 P-Channel QFET® MOSFET Package Dimensions TO-220 Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation FQP17P10 Rev.C0 7 ww.fairchildsemi.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.