Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQP50N06, MOSFET

FQP50N06

QFET

FQP50N06

60V N-Channel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as automotive, DC/

DC converters, and high efficiency switching for power

management in portable and battery operated products.

Features

• 50A, 60V, R

DS(on)

= 0.022Ω @V

= 10 V

• Low gate charge ( typical 31 nC)

• Low Crss ( typical 65 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

• 175°C maximum junction temperature rating

Absolute Maximum Ratings T

= 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter FQP50N06 Units

DSS

Drain-Source Voltage 60 V

Drain Current

- Continuous (T

= 25°C)

50 A

- Continuous (T

= 100°C)

35.4 A

Drain Current - Pulsed

(Note 1)

200 A

GSS

Gate-Source Voltage ± 25 V

Single Pulsed Avalanche Energy

(Note 2)

490 mJ

Avalanche Current

(Note 1)

50 A

Repetitive Avalanche Energy

(Note 1)

12 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

7.0 V/ns

Power Dissipation (T

= 25°C)

120 W

- Derate above 25°C 0.8 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +175 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds

300 °C

Symbol Parameter Typ Max Units

θJC

Thermal Resistance, Junction-to-Case -- 1.24 °C/W

θCS

Thermal Resistance, Case-to-Sink 0.5 -- °C/W

θJA

Thermal Resistance, Junction-to-Ambient -- 62.5 °C/W

TO-220

FQP Series

Summary of content (8 pages)

PAGE 1
TM FQP50N06 60V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode.
PAGE 2
Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 -- -- V ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C -- 0.
PAGE 3
FQP50N06 Typical Characteristics VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : ID, Drain Current [A] 2 10 ID, Drain Current [A] 2 10 1 10 1 10 175℃ 25℃ ※ Note : 1. 250μ s Pulse Test 2. TC = 25℃ 0 ※ Notes : 1. VDS = 30V 2. 250μ s Pulse Test -55℃ 10 0 -1 0 10 10 1 10 2 10 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.05 2 VGS = 10V 0.
PAGE 4
(Continued) 1.2 2.5 2.0 1.1 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage FQP50N06 Typical Characteristics 1.5 1.0 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 0.5 150 ※ Notes : 1. VGS = 10 V 2. ID = 25 A 0.0 -100 200 -50 10 150 200 Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQP50N06 Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% tr td(on) td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2003 Fairchild Semiconductor Corporation ID (t) VDS (t) VDD tp Time Rev.
PAGE 6
FQP50N06 Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2003 Fairchild Semiconductor Corporation Rev.
PAGE 7
FQP50N06 Package Dimensions TO-220 4.50 ±0.20 2.80 ±0.10 (3.00) +0.10 1.30 –0.05 18.95MAX. (3.70) ø3.60 ±0.10 15.90 ±0.20 1.30 ±0.10 (8.70) (1.46) 9.20 ±0.20 (1.70) 9.90 ±0.20 1.52 ±0.10 0.80 ±0.10 2.54TYP [2.54 ±0.20] 10.08 ±0.30 (1.00) 13.08 ±0.20 ) (45° 1.27 ±0.10 +0.10 0.50 –0.05 2.40 ±0.20 2.54TYP [2.54 ±0.20] 10.00 ±0.20 Dimensions in Millimeters ©2003 Fairchild Semiconductor Corporation Rev.
PAGE 8
TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ Bottomless™ FAST® FASTr™ CoolFET™ CROSSVOLT™ FRFET™ GlobalOptoisolator™ DOME™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ EnSigna™ I2C™ Across the board. Around the world.