Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsFQP55N10, MOSFET

November 2013

FQP55N10 — N-Channel QFET

MOSFET

FQP55N10 Rev. C1

www.fairchildsemi.com

FQP55N10

Description

This N-Channel enhancement mode power MOSFET is pro-

duced using Fairchild Semiconductor’s proprietary planar stripe

and DMOS technology. This advanced MOSFET technology has

been especially tailored to reduce on-state resistance, and to

provide superior switching performance and high avalanche en-

ergy strength. These devices are suitable for switched mode

power supplies, audio amplifier, DC motor control, and variable

switching power applications.

Features

• 55 A, 100 V, R

DS(on)

= 26 mΩ (Max.) @ V

= 10 V,

= 27.5 A

• Low Gate Charge (Typ. 75 nC)

• Low Crss (Typ. 130 pF)

• 100% Avalanche Tested

•175°C Maximum Junction Temperature Rating

TO-220

N-Channel QFET

MOSFET

100 V, 55 A, 26 mΩ

Absolute Maximum Ratings T

= 25°C unless otherwise noted.

Thermal Characteristics

Symbol Parameter FQP55N10 Unit

DSS

Drain-Source Voltage 100 V

Drain Current

- Continuous (T

= 25°C)

55 A

- Continuous (T

= 100°C)

38.9 A

Drain Current - Pulsed

(Note 1)

220 A

GSS

Gate-Source Voltage ± 25 V

Single Pulsed Avalanche Energy

(Note 2)

1100 mJ

Avalanche Current

(Note 1)

55 A

Repetitive Avalanche Energy

(Note 1)

15.5 mJ

dv/dt Peak Diode Recovery dv/dt

(Note 3)

6.0 V/ns

Power Dissipation (T

= 25°C)

155 W

- Derate above 25°C 1.03 W/°C

, T

STG

Operating and Storage Temperature Range -55 to +175 °C

Maximum Lead Temperature for Soldering,

1/8" from Case for 5 seconds

300 °C

Symbol Parameter FQP55N10 Unit

θJC

Thermal Resistance, Junction-to-Case, Max. 0.97 °C/W

θJA

Thermal Resistance, Junction-to-Ambient, Max. 62.5 °C/W

Summary of content (8 pages)

PAGE 1
FQP55N10 N-Channel QFET® MOSFET 100 V, 55 A, 26 mΩ Description Features This N-Channel enhancement mode power MOSFET is produced using Fairchild Semiconductor’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on-state resistance, and to provide superior switching performance and high avalanche energy strength.
PAGE 2
Part Number FQP55N10 Top Mark FQP55N10 Electrical Characteristics Symbol Package TO-220 Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units TC = 25°C unless otherwise noted. Parameter Test Conditions Min Typ Max Unit 100 -- -- V -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 μA ΔBVDSS / ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, Referenced to 25°C -- 0.
PAGE 3
VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : ID, Drain Current [A] 2 10 ID, Drain Current [A] 2 10 1 10 ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ 1 10 175℃ 25℃ 0 10 ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test -55℃ 0 -1 10 -1 10 0 10 1 10 2 10 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.
PAGE 4
(Continued) 3.0 RDS(ON), (Normalized) Drain-Source On-Resistance BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.5 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 27.5 A 0.5 0.0 -100 200 -50 0 o 50 100 150 200 o TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs.
PAGE 5
FQP55N10 — N-Channel QFET® MOSFET Figure 12. Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ 200nF 12V Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 13. Resistive Switching Test Circuit & Waveforms VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on tf t off Figure 14.
PAGE 6
FQP55N10 — N-Channel QFET® MOSFET Figure 15.
PAGE 7
FQP55N10 — N-Channel QFET® MOSFET Mechanical Dimensions Figure 16. TO220, Molded, 3-Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.