Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Switch FET bus switch Single supply SOIC 14

March 2008

FST3125 • Rev. 1.0.3

FST3125 — 4-Bit Bus Switch

Features



4Ω Switch Connection between Two Ports

 Minimal Propagation Delay through the Switch

 Low I

 Zero Bounce in Flow-through Mode

 Control Inputs Compatible with TTL Level

Description

Fairchild switch FST3125 provides four high-speed

CMOS TTL-compatible bus switches. The low on

resistance of the switch allows inputs to be connected

to outputs without adding propagation delay or

generating additional ground bounce noise.

The device is organized as four one1-bit switches with

separate /OE inputs. When /OE is LOW, the switch is

ON and port A is connected to port B. When /OE is

HIGH, the switch is OPEN and a high-impedance state

exists between the two ports.

Ordering Information

Part Number

Operating

Temperature

Range

Package

Packing

Method

FST3125M

-40 to 85°C

14-Lead, Small Outline Integrated Circuit (SOIC) 0.150 inch

Narrow

Tube

FST3125MX

-40 to 85°C

14-Lead, Small Outline Integrated Circuit (SOIC) 0.150 inch

Narrow

Tape and Reel

FST3125QSC

-40 to 85°C

16-Lead, Quarter Size Outline Package (QSOP) MO-137

0.150 inch Wide

Tube

FST3125QSCX

-40 to 85°C

16-Lead, Quarter Size Outline Package (QSOP) MO-137

0.150 inch Wide

Tape and Reel

FST3125MTC

-40 to 85°C

14-Lead, Thin Shrink Small Outline Package (TSSOP)

MO-153, 4mm Wide

Tube

FST3125MTCX

-40 to 85°C

14-Lead, Thin Shrink Small Outline Package (TSSOP)

MO-153, 4mm Wide

Tape and Reel

All packages are lead free per JEDEC: J-STD-020B standard.

The Fairchild switch family derives from and embodies Fairchild’s proven switch technology used for several years in its

74LVX3L384 (FST3384) bus switch product.

Figure 1. Logic Diagram

Summary of content (9 pages)

PAGE 1
FST3125 — 4-Bit Bus Switch Features Description Fairchild switch FST3125 provides four high-speed CMOS TTL-compatible bus switches. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.
PAGE 2
/OE1 1 14 VCC 1A 2 13 /OE4 1B 3 12 4A /OE2 4 11 4B 2A 5 10 /OE3 6 2B 9 7 GND 8 NC 1 16 VCC /OE1 2 15 /OE4 1A 3 14 4A 1B 4 13 4B /OE2 5 12 /OE3 2A 6 11 3A 2B 7 10 3B GND 8 9 NC FST3125 — 4-Bit Bus Switch Pin Configurations 3A 3B Figure 2. SOIC and TSSOP Pin Assignments Figure 3.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage Min. Max. Unit -0.5 7.0 V VS DC Switch Voltage -0.5 7.
PAGE 4
Typical values are at VCC = 5.0V and TA = 25°C. Symbol VIK Parameter Conditions Clamp Diode Voltage VCC (V) IIN = -18mA TA=-40 to +85°C Min. Typ. Units Max. 4.5 -1.2 V VIH High-Level Input Voltage 4.0 to 5.5 VIL Low-Level Input Voltage 4.0 to 5.5 0.8 V IIN Input Leakage Current 0 ≤ VIN ≤ 5.5 5.5 ±1.0 µA IOZ Off-state Leakage Current 0 ≤ A, B ≤ VCC 5.5 ±1.0 µA VIN = 0V, IIN = 64mA 4.5 4 7 VIN = 0V, IIN = 30mA 4.5 4 7 VIN = 2.4V, IIN = 15mA 4.
PAGE 5
FST3125 — 4-Bit Bus Switch AC Loadings and Waveforms Notes: Input driven by 50Ω source terminated in 50Ω. CL includes load and stray capacitance. Input PRR = 1.0MHz, tw = 500ns. Figure 4. AC Test Circuit Figure 5. AC Waveforms © 2005 Fairchild Semiconductor Corporation FST3125 • Rev. 1.0.3 www.fairchildsemi.
PAGE 6
FST3125 — 4-Bit Bus Switch Physical Dimensions 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 1.27 LAND PATTERN RECOMMENDATION C B A M (0.33) 1.75 MAX 1.50 1.25 SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS.
PAGE 7
FST3125 — 4-Bit Bus Switch Physical Dimensions LAND PATTERN RECOMMENDATION TOP VIEW END VIEW SIDE VIEW DETAIL A Figure 7. 16-Lead, Quarter-Size Outline Package (QSOP), MO-1370.150-inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
FST3125 — 4-Bit Bus Switch Physical Dimensions 0.65 0.43 TYP 1.65 6.10 0.45 12.00°TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 8.