Datasheet

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December 2012

FST3345 • Rev. 1.0.3

FST3345 — 8-Bit Bus Switch

Features

 4 Ω Switch Connection between Two Ports

 Minimal Propagation Delay through the Switch

 Low I

 Zero Bounce in Flow-through Mode

 Control Inputs Compatible with TTL Level

Description

The FST3345 switch provides eight-bits of high-speed

CMOS TTL-compatible bus switching. The low on

resistance of the switch allows inputs to be connected to

outputs without adding propagation delay or generating

additional ground bounce noise.

The device is organized as an eight-bit switch with dual

output enable inputs (OE and /OE). When /OE is LOW

or OE is HIGH, the switch is ON and port A is connected

to port B. When /OE is HIGH, and OE is LOW, the

switch is OPEN and a high-impedance state exists

between the two ports.

Ordering Information

Part Number

Operating

Temperatur

e Range

Package

Packing

Method

FST3345MTCX -40 to +85°C

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC

MO-153, 4.4 mm Wide

Tape and Reel

Logic Diagram

/OE

Figure 1. Logic Diagram

Summary of content (7 pages)

PAGE 1
FST3345 — 8-Bit Bus Switch Features Description      The FST3345 switch provides eight-bits of high-speed CMOS TTL-compatible bus switching. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.
PAGE 2
FST3345 — 8-Bit Bus Switch Pin Configuration OE 1 20 VCC A0 2 19 /OE A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 GND 10 11 B7 Figure 2.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.5 7.0 V 7.0 V VCC Supply Voltage VS DC Switch Voltage -0.
PAGE 4
Typical values are at VCC = 5.0 V and TA = 25°C. Symbol Parameter Conditions VIK Clamp Diode Voltage VIH High-Level Input Voltage 4.0 to 5.5 VIL Low-Level Input Voltage IIN Input Leakage Current IOZ RON ICC ΔICC TA=-40 to +85°C VCC (V) IIN = -18 mA Min. Typ. Max. 4.5 Units -1.2 V 4.0 to 5.5 0.8 V 0 ≤ VIN ≤ 5.5 V 5.5 ±1.0 µA Off-state Leakage Current 0 ≤ A, B ≤ VCC 5.5 ±1.0 µA 2.0 V VIN = 0 V, IIN = 64 mA 4.5 4 7 VIN = 0 V, IIN = 30 mA 4.5 4 7 VIN = 2.
PAGE 5
FST3345 — 8-Bit Bus Switch AC Loadings and Waveforms Notes: Input driven by 50 Ω source terminated in 50 Ω. CL includes load and stray capacitance. Input PRR = 1.0 MHz, tw = 500 ns. Figure 3. AC Test Circuit Figure 4. AC Waveforms © 1997 Fairchild Semiconductor Corporation FST3345 • Rev. 1.0.3 www.fairchildsemi.
PAGE 6
FST3345 — 8-Bit Bus Switch Physical Dimensions Figure 5. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4 mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.