Datasheet

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March 2012

FXLA101 • Rev. 1.0.4

FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing

FXLA101

Low-Voltage Dual-Supply 1-Bit Voltage Translator with

Auto Direction Sensing

Features

 Bi-Directional Interface between Two Levels:

from 1.1V to 3.6V

 Fully Configurable: Inputs and Outputs Track V

 Non-Preferential Power-Up; Either V

May Be

Powered Up First

 Outputs Switch to 3-State if Either V

is at GND

 Power-Off Protection

 Bus-Hold on Data Inputs Eliminates the Need for

Pull-Up Resistors; Do Not Use Pull-Up Resistors on

A or B Ports

 Control Input (/OE) Referenced to V

CCA

Voltage

 Packaged in MicroPak™ 6 (1.00mm x 1.45mm)

 Direction Control Not Necessary

 100Mbps Throughput when Translating Between

1.8V and 2.5V

 ESD Protection Exceeds:

- 8kV HBM (per JESD22-A114 & Mil Std 883e

3015.7)

- 2kV CDM (per ESD STM 5.3)

Applications

 Cell Phones, PDAs, Digital Cameras, Portable GPS

Description

The FXLA101 is a configurable dual-voltage supply

translator for both uni-directional and bi-directional

voltage translation between two logic levels. The device

allows translation between voltages as high as 3.6V to

as low as 1.1V. The A port tracks the V

CCA

level and the

B port tracks the V

CCB

level. This allows for bi-directional

voltage translation over a variety of voltage levels: 1.2V,

1.5V, 1.8V, 2.5V, and 3.3V.

The device remains in three-state as long as either

=0V, allowing either V

to be powered up first.

Internal power-down control circuits place the device in

3-state if either V

is removed.

The /OE input, when HIGH, disables both the A and B

ports by placing them in a 3-state condition. The /OE

input is supplied by V

CCA

The FXLA101 supports bi-directional translation without

the need for a direction control pin. The two ports of the

device have auto-direction sense capability. Either port

may sense an input signal and transfer it as an output

signal to the other port.

Ordering Information

Part Number

Top

Mark

Operating

Temperature

Range

Package

Packing

Method

FXLA101L6X XK

-40 to 85°C

6-Lead MicroPak™1.00mm x 1.45mm Package

5K Units Tape

and Reel

FXLA101FHX XK 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

Summary of content (18 pages)

PAGE 1
FXLA101 Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Features Description  Bi-Directional Interface between Two Levels: from 1.1V to 3.6V   Fully Configurable: Inputs and Outputs Track VCC    Outputs Switch to 3-State if Either VCC is at GND     Control Input (/OE) Referenced to VCCA Voltage  ESD Protection Exceeds: - 8kV HBM (per JESD22-A114 & Mil Std 883e 3015.7) - 2kV CDM (per ESD STM 5.
PAGE 2
Figure 1. Pin Configuration (Top Through View) Pin Definitions Pin # Name Description 1 VCCA A-Side Power Supply 2 GND Ground 3 A A Side Input or 3-State Output 4 B B Side Input or 3-State Output 5 /OE Output Enable Input 6 VCCB B Side Power supply © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Pin Configuration www.fairchildsemi.
PAGE 3
Figure 2. Functional Diagram Function Table Control Outputs /OE L Normal Operation H 3-State H = HIGH Logic Level L = LOW Logic Level © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.4 FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Direction Sensing Functional Diagram www.fairchildsemi.
PAGE 4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
PAGE 5
FXL translators offer an advantage in that either VCC may be powered up first. This benefit derives from the chip design. When either VCC is at 0V, outputs are in a high-impedance state. The control input (/OE) is designed to track the VCCA supply. A pull-up resistor tying /OE to VCCA should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power-up or power-down.
PAGE 6
TA=-40 to 85°C. Symbol Parameter Conditions Data Inputs An Control Pin /OE VIHA VCCB (V) Data Inputs Bn Min. 2.70 to 3.60 2.00 2.30 to 2.70 1.60 1.65 to 2.30 1.10 to 3.60 .65xVCCA 1.40 to 1.65 .65xVCCA 1.10 to 1.40 High-Level Input Voltage VIHB VCCA (V) Typ. .90xVCCA 2.70 to 3.60 2.00 2.30 to 2.70 1.60 1.10 to 3.60 1.65 to 2.30 .65xVCCB 1.40 to 1.65 .65xVCCB 1.10 to 1.40 .90xVCCB V .80 2.30 to 2.70 Data Inputs An Control Pin /OE VILB VOHA VOHB VOLA VOLB .35xVCCA 1.
PAGE 7
TA=-40 to 85°C. Symbol II(ODH) II(ODL) II IOFF IOZ ICCA/B ICCZ Parameter Bus-Hold Input Overdrive High Current(4) Bus-Hold Input Overdrive Low (5) Current Input Leakage Current Power-Off Leakage Current 3-State Output Leakage Quiescent Supply Current(6, 7) ICCA Quiescent Supply Current ICCB Conditions VCCA (V) VCCB (V) Min. Max. 3.60 3.60 450.00 2.70 2.70 300.00 1.95 1.95 200.00 1.60 1.60 120.00 1.40 1.40 80.00 3.60 3.60 -450.00 2.70 2.70 -300.00 1.95 1.95 -200.
PAGE 8
A Port (An) Output Load: CL=15pF, RL ≥ MΩ (CI/O=4pF), TA=-40 to 85°C Symbol Parameter VCCA=3.0V to 3.6V Typ. Max. VCCA=2.3V to 2.7V Typ. VCCA=1.65V to 1.95V Max. Typ. Max VCCA=1.4V to 1.6V Typ. VCCA=1.1V to 1.3V Max. Typ. Units trise Output Rise Time A Port(9) 3.0 3.5 4.0 5.0 7.5 ns tfall Output Fall Time A (10) Port 3.0 3.5 4.0 5.0 7.5 ns IOHD Dynamic Output Current (9) High -11.4 -7.5 -4.7 -3.2 -1.7 mA IOLD Dynamic Output Current Low(10) +11.4 +7.5 +4.7 +3.2 +1.
PAGE 9
VCCA = 3.0V to 3.6V, TA=-40 to 85°C Symbol tPLH,tPHL Parameter VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units Min. Max. Min. Max. Min. Max Min. Max. Typ. A to B 0.2 4.0 0.3 4.2 0.5 5.4 0.6 6.8 6.9 ns B to A 0.2 4.0 0.2 4.1 0.3 5.0 0.5 6.0 4.5 ns tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs tSKEW A Port, (11) B Port 0.5 0.5 0.5 1.0 1.0 ns VCCB=1.1V to 1.3V Units VCCA = 2.3V to 2.
PAGE 10
VCCA = 1.4V to 1.6V, TA=-40 to 85°C Symbol tPLH,tPHL VCCB=3.0V to 3.6V Parameter VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Units Min. Max. Min. Max. Min. Max Min. Max. Typ. A to B 0.5 6.0 0.5 6.5 1.0 7.0 1.0 8.5 7.9 ns B to A 0.6 6.8 0.8 6.9 0.9 7.5 1.0 8.5 6.1 ns tPZL,tPZH /OE to A, /OE to B 1.7 1.7 1.7 1.7 1.7 µs tSKEW A Port, (12) B Port 1.0 1.0 1.0 1.0 1.0 ns Units VCCA = 1.1V to 1.
PAGE 11
TA=-40 to 85°C. VCCB=3.0V to 3.6V VCCB=2.3V to 2.7V VCCB=1.65V to 1.95V VCCB=1.4V to 1.6V VCCB=1.1V to 1.3V Min. Min. Min. Min. Typ. VCCA=3.00V to 3.60V 140 120 100 80 40 Mbps VCCA=2.30V to 2.70V 120 120 100 80 40 Mbps VCCA=1.65V to 1.95V 100 100 80 60 40 Mbps VCCA=1.40V to 1.60V 80 80 60 60 40 Mbps Typ. Typ. Typ. Typ. Typ. 40 40 40 40 40 VCCA VCCA=1.10V to 1.30V Units Mbps Notes: 13. Maximum data rate is guaranteed, but not tested. 14.
PAGE 12
hold.” “Static Mode” is when only the bus hold drives the channel. The bus hold can be over ridden in the event of a direction change. The strong driver allows the FXLA101 to quickly charge and discharge capacitive transmission lines during dynamic mode. Static mode conserves power, where ICC is typically < 5µA. The FXLA101 I/O architecture benefits the end user, beyond level translation, in the following three ways: Auto Direction without an external direction pin. Drive Capacitive Loads.
PAGE 13
VCC TEST SIGNAL DUT C1 R1 Figure 3. Test Circuit Table 1. Table 2. AC Test Conditions Test Input Signal Output Enable Control tPLH, tPHL Data Pulses 0V tPZL 0V HIGH to LOW Switch tPZH VCCI HIGH to LOW Switch AC Load VCCO C1 R1 1.2V± 0.1V 15pF 1MΩ 1.5V± 0.1V 15pF 1MΩ 1.8V ± 0.15V 15pF 1MΩ 2.5V ± 0.2V 15pF 1MΩ 3.3V ± 0.3V 15pF 1MΩ DATA IN Vmi VCCI GND tpxx tpxx DATA OUT Vmo VCCO Figure 4.
PAGE 14
Notes: 17. Input tR = tF = 2.0ns, 10% to 90%. 18. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. Figure 6. 3-State Output High Enable Time for Low Voltage Logic Notes: 19. Input tR = tF = 2.0ns, 10% to 90%. 20. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only. Table 3. Test Measure Points Symbol VMI VDD (21) VCCI /2 VMO VCCo /2 VX 0.9 x VCCo VY 0.1 x VCCo FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing Figure 5.
PAGE 15
VOH 80% x VCCO VOUT 20% x VCCO VOL Time IOHD ≈ (CL + CI / O ) × ΔVOUT (20% − 80%) • VCCO = (CL + CI / O ) × Δt t RISE Figure 7. Active Output Rise Time and Dynamic Output Current High VOH tfall 80% x VCCO VOUT 20% x VCCO VOL Time IOLD ≈ (CL + CI / O ) × ΔVOUT (80% − 20%) • VCCO = (CL + CI / O ) × Δt t FALL Figure 8. Active Output Fall Time and Dynamic Output Current Low tW VCCI DATA IN VCCI/2 VCCI/2 GND Maximum Data Rate, f = 1/tW Figure 9.
PAGE 16
2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X BOTTOM VIEW 0.075 X 45 CHAMFER DETAIL A PIN 1 TERMINAL (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.
PAGE 17
0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C.
PAGE 18
FLXA101 — Low-Voltage Dual-Supply 1-Bit Voltage Translator with Auto Detection Sensing 18 www.fairchildsemi.com © 2009 Fairchild Semiconductor Corporation FLXA101 • Rev. 1.0.