Datasheet

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HUF75321P3

N-Channel UltraFET Power MOSFET

55 V, 35 A, 34 mΩ

These N-Channel power MOSFETs are manufactured

using the innovative UltraFET process. This advanced

process technology achieves the lowest possible on-

resistance per silicon area, resulting in outstanding

performance. This device is capable of withstanding high

energy in the avalanche mode and the diode exhibits very

low reverse recovery time and stored charge. It was

designed for use in applications where power efficiency is

important, such as switching regulators, switching

converters, motor drivers, relay drivers, low-voltage bus

switches, and power management in portable and battery-

operated products.

Formerly developmental type TA75321.

Features

• 35A, 55V

• Simulation Models

- Temperature Compensated PSPICE® and SABER™

Models

- Thermal Impedance SPICE and SABER Models

Available on the WEB at: www.fairchildsemi.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

Components to PC Boards”

Packaging

JEDEC TO-220AB

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

For severe environments, see our Automotive HUFA series.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75321P3 TO-220AB 75321P

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

Data Sheet

October 2013

Symbol

Summary of content (10 pages)

PAGE 1
HUF75321P3 October 2013 Data Sheet N-Channel UltraFET Power MOSFET 55 V, 35 A, 34 mΩ Features • 35A, 55V These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge.
PAGE 2
HUF75321P3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS V V V 55 55 ±20 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . .
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HUF75321P3 TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 680 - pF - 270 - pF - 60 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 35A - - 1.
PAGE 4
HUF75321P3 Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 500 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 100 150 VGS = 20V VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4.
PAGE 5
HUF75321P3 Typical Performance Curves 1.2 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 35A VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 (Continued) 2.0 1.5 1.0 0.5 -80 -40 0 40 80 120 160 1.0 0.8 0.6 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10.
PAGE 6
HUF75321P3 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17.
PAGE 7
HUF75321P3 PSPICE Electrical Model .SUBCKT HUF75321P 2 1 3 ; rev 4/29/98 CA 12 8 9.96e-10 CB 15 14 9.83e-10 CIN 6 8 6.18e-10 LDRAIN DPLCAP DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 DBREAK + RSLC2 5 51 ESLC 11 - LDRAIN 2 5 1e-9 LGATE 1 9 3.57e-9 LSOURCE 3 7 4.25e-9 RLDRAIN RSLC1 51 EBREAK 11 7 17 18 59.
PAGE 8
HUF75321P3 SABER Electrical Model REV April 1998 template huf75321p n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 7.47e-13, cjo = 1.02e-9, tt = 3.21e-8, m = 0.5) d..model dbreakmod = () d..model dplcapmod = (cjo = 9e-10, is = 1e-30, n = 10, m = 0.85) m..model mmedmod = (type=_n, vto = 3.25, kp = 1.75, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.65, kp = 32, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.91, kp = 0.07, is = 1e-30, tox = 1) sw_vcsp..
PAGE 9
HUF75321P3 SPICE Thermal Model th JUNCTION REV 24 February 1999 HUF75321P CTHERM1 th 6 2.7e-3 CTHERM2 6 5 3.7e-3 CTHERM3 5 4 1.2e-2 CTHERM4 4 3 3.8e-3 CTHERM5 3 2 1.4e-2 CTHERM6 2 tl 10.55 RTHERM1 RTHERM1 th 6 1.10e-2 RTHERM2 6 5 2.72e-2 RTHERM3 5 4 7.67e-2 RTHERM4 4 3 4.30e-1 RTHERM5 3 2 6.49e-1 RTHERM6 2 tl 8.61e-2 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75321P template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.7e-3 ctherm.
PAGE 10
HUF75321P3 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.