Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsHUF75344P3, MOSFET

HUF75344G3, HUF75344P3 Rev. C0

HUF75344G3, HUF75344P3

N-Channel UltraFET Power MOSFET

55 V, 75 A, 8 mΩ

These N-Channel power MOSFETs are manufactured

using the innovative UltraFET process. This advanced

process technology achieves the lowest possible on-

resistance per silicon area, resulting in outstanding

performance. This device is capable of withstanding high

energy in the avalanche mode and the diode exhibits very

low reverse recovery time and stored charge. It was

designed for use in applications where power efficiency is

important, such as switching regulators, switching

converters, motor drivers, relay drivers, low-voltage bus

switches, and power management in portable and battery-

operated products.

Formerly developmental type TA75344.

Features

• 75A, 55V

• Simulation Models

- Temperature Compensated PSPICE® and SABER™

Models

- Thermal Impedance PSPICE and SABER Models

Available on the web at: www.fairchildsemi.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Moun

Components to PC Boards”

Symbol

Packaging

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

For severe environments, see our Automotive HUFA series.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75344G3 TO-247 75344G

HUF75344P3 TO-220AB 75344P

JEDEC STYLE TO-247 JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN

(TAB)

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

Data Sheet

October 2013

Summary of content (10 pages)

PAGE 1
HUF75344G3, HUF75344P3 Data Sheet N-Channel UltraFET Power MOSFET 55 V, 75 A, 8 mΩ These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge.
PAGE 2
HUF75344G3, HUF75344P3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS V V V 55 55 ±20 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . .
PAGE 3
HUF75344G3, HUF75344P3 Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 75A - - 1.25 V trr ISD = 75A, dISD/dt = 100A/µs - - 105 ns QRR ISD = 75A, dISD/dt = 100A/µs - - 210 nC VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS Typical Performance Curves 80 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 60 40 20 0.
PAGE 4
HUF75344G3, HUF75344P3 Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 2000 TC = 25oC 1000 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 20V VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4.
PAGE 5
HUF75344G3, HUF75344P3 Typical Performance Curves (Continued) 1.2 VGS = VDS, ID = 250µA PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 75A NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 0.5 -80 0 -40 40 80 120 0.8 0.6 0.4 -80 200 160 1.0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 10.
PAGE 6
HUF75344G3, HUF75344P3 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS VGS = 20V Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17.
PAGE 7
HUF75344G3, HUF75344P3 PSPICE Electrical Model .SUBCKT HUF75337 2 1 3 ; rev 3 Feb 1999 CA 12 8 4.9e-9 CB 15 14 4.75e-9 CIN 6 8 2.85e-9 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - EBREAK 11 7 17 18 59.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 RLDRAIN RSLC1 51 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.6e-9 LSOURCE 3 7 1.
PAGE 8
HUF75344G3, HUF75344P3 SABER Electrical Model REV 3 February 1999 template huf75344 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 2.95e-12, cjo = 5.19e-9, tt = 5.90e-8, m = 0.55) d..model dbreakmod = () d..model dplcapmod = (cjo = 5.40e-9, is = 1e-30, n = 1, m = 0.88) m..model mmedmod = (type=_n, vto = 3.29, kp = 5.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.83, kp = 123, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.90, kp = 0.
PAGE 9
HUF75344G3, HUF75344P3 SPICE Thermal Model th JUNCTION REV 5 February 1999 HUF75344 CTHERM1 th 6 5.0e-3 CTHERM2 6 5 1.0e-2 CTHERM3 5 4 1.3e-2 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 2.2e-2 CTHERM6 2 tl 8.5e-2 RTHERM1 RTHERM1 th 6 6.0e-4 RTHERM2 6 5 3.5e-3 RTHERM3 5 4 2.5e-2 RTHERM4 4 3 4.8e-2 RTHERM5 3 2 1.6e-1 RTHERM6 2 tl 1.8e-1 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75344 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 5.
PAGE 10
HUF75344G3, HUF75344P3 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.