Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsHUF75345P3, MOSFET

HUF75345G3, HUF75345P3, HUF75345S3S Rev. C0

HUF75345G3, HUF75345P3, HUF75345S3S

N-Channel UltraFET Power MOSFET

55 V, 75 A, 7 m

Ω

These N-Channel power MOSFETs are manufactured using

the innovative UltraFET process. This advanced process

technology achieves the lowest possible on-resistance per

silicon area, resulting in outstanding performance. This

device is capable of withstanding high energy in the

avalanche mode and the diode exhibits very low reverse

recovery time and stored charge. It was designed for use in

applications where power efficiency is important, such as

switching regulators, switching converters, motor drivers,

relay drivers, low-voltage bus switches, and power

management in portable and battery-operated products.

Formerly developmental type TA75345.

Features

• 75A, 55V

• Simulation Models

- Temperature Compensated PSPICE® and SABER™

Models

- Thermal Impedance SPICE and SABER Models

Available on the WEB at: www.fairchildsemi.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

For severe environments, see our Automotive HUFA series.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75345G3 TO-247 75345G

HUF75345P3 TO-220AB 75345P

HUF75345S3ST

TO-263AB 75345S

JEDEC STYLE TO-247 JEDEC TO-220AB

JEDEC TO-263AB

SOURCE

DRAIN

GATE

DRAIN

(TAB)

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

(FLANGE)

Data Sheet

October 2013

Summary of content (11 pages)

PAGE 1
HUF75345G3, HUF75345P3, HUF75345S3S October 2013 Data Sheet Features N-Channel UltraFET Power MOSFET 55 V, 75 A, 7 mΩ • 75A, 55V These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge.
PAGE 2
HUF75345G3, HUF75345P3, HUF75345S3S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 55 Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 55 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
HUF75345G3, HUF75345P3, HUF75345S3S TC = 25oC, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 4000 - pF - 1450 - pF - 450 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD MIN TYP MAX UNITS ISD = 75A - - 1.
PAGE 4
HUF75345G3, HUF75345P3, HUF75345S3S Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 2000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 1000 175 - TC I = I25 150 VGS = 20V VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4.
PAGE 5
HUF75345G3, HUF75345P3, HUF75345S3S Typical Performance Curves (Continued) 1.2 PULSE DURATION = 80µs, VGS = 10V, ID = 75A DUTY CYCLE = 0.5% MAX VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 0.5 -80 -40 0 40 80 120 160 1.0 0.8 0.6 0.4 -80 200 -40 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 200 FIGURE 10.
PAGE 6
HUF75345G3, HUF75345P3, HUF75345S3S Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + - VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17.
PAGE 7
HUF75345G3, HUF75345P3, HUF75345S3S PSPICE Electrical Model rev 3 Feb 99 CA 12 8 5.55e-9 CB 15 14 5.55e-9 CIN 6 8 3.45e-9 LDRAIN DPLCAP 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD RLDRAIN RSLC1 51 RSLC2 5 51 EBREAK 11 7 17 18 56.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 DBREAK ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.6e-9 LSOURCE 3 7 1.1e-9 KGATE LSOURCE LGATE 0.
PAGE 8
HUF75345G3, HUF75345P3, HUF75345S3S SABER Electrical Model REV 3 February 1999 template huf75345 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 6e-12, xti = 5, cjo = 5.5e-9, tt = 5.9e-8, m=0.5, vj=0.75) d..model dbreakmod = () d..model dplcapmod = (cjo = 6.75e-9, is = 1e-30, m = 0.88, vj = 1.45,fc=0.5) m..model mmedmod = (type=_n, vto = 2.93, kp = 13.75, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.23, kp = 96, is=1e-30,tox=1, lambda = 0.06) DPLCAP m..
PAGE 9
HUF75345G3, HUF75345P3, HUF75345S3S SPICE Thermal Model th JUNCTION REV 5 February 1999 HUF75345 CTHERM1 th 6 6.3e-3 CTHERM2 6 5 1.5e-2 CTHERM3 5 4 2.0e-2 CTHERM4 4 3 3.0e-2 CTHERM5 3 2 8.0e-2 CTHERM6 2 tl 1.5e-1 RTHERM1 RTHERM1 th 6 5.0e-3 RTHERM2 6 5 1.8e-2 RTHERM3 5 4 5.0e-2 RTHERM4 4 3 8.5e-2 RTHERM5 3 2 1.0e-1 RTHERM6 2 tl 1.1e-1 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75345 template thermal_model th tl thermal_c th, tl { ctherm.
PAGE 10
HUF75345G3, HUF75345P3, HUF75345S3S Mechanical Dimensions TO-220 3L Figure 20. TO-220, Molded, 3Lead, Jedec Variation AB Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 11
HUF75345G3, HUF75345P3, HUF75345S3S TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.