Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsHUF75639P3, MOSFET

HUF75639G3, HUF75639P3, HUF75639S3S,

HUF75639S3

N-Channel UltraFET Power MOSFET

100 V, 56 A, 25 mΩ

These N-Channel power MOSFETs are manufactured

using the innovative UltraFET process. This advanced

process technology achieves the lowest possible on-

resistance per silicon area, resulting in outstanding

performance. This device is capable of withstanding high

energy in the avalanche mode and the diode exhibits very

low reverse recovery time and stored charge. It was

designed for use in applications where power efficiency is

important, such as switching regulators, switching

converters, motor drivers, relay drivers, low-voltage bus

switches, and power management in portable and battery-

operated products.

Formerly developmental type TA75639.

Features

• 56A, 100V

• Simulation Models

- Temperature Compensated PSPICE® and SABER™

Electrical Models

- Spice and Saber Thermal Impedance Models

- www.fairchildsemi.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

Components to PC Boards”

Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html

For severe environments, see our Automotive HUFA series.

All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF75639G3 TO-247 75639G

HUF75639P3 TO-220AB 75639P

HUF75639S3ST

TO-263AB 75639S

HUF75639S3 TO-262AA 75639S

Packaging

JEDEC STYLE TO-247 JEDEC TO-220AB

JEDEC TO-263AB TO-262AA

SOURCE

DRAIN

GATE

DRAIN

(TAB)

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

(FLANGE)

DRAIN

SOURCE

GATE

DRAIN

(TAB)

Data Sheet

October 2013

Symbol

Summary of content (10 pages)

PAGE 1
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Data Sheet N-Channel UltraFET Power MOSFET 100 V, 56 A, 25 mΩ These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge.
PAGE 2
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS V V V 100 100 ±20 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 2000 - pF - 500 - pF - 65 - pF CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 56A - - 1.
PAGE 4
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Typical Performance Curves (Continued) IDM , PEAK CURRENT (A) 1000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 100 VGS = 10V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4.
PAGE 5
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Typical Performance Curves 1.2 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 56A VGS = VDS, ID = 250µA NORMALIZED GATE 2.5 2.0 1.5 1.0 THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 3.0 (Continued) 1.0 0.8 0.5 0 0.6 -80 -40 0 40 80 120 160 200 -80 -40 TJ, JUNCTION TEMPERATURE (oC) 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9.
PAGE 6
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17.
PAGE 7
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 PSPICE Electrical Model SUBCKT HUF75639 2 1 3 ; rev Oct. 98 CA 12 8 2.8e-9 CB 15 14 2.65e-9 CIN 6 8 1.9e-9 LDRAIN DPLCAP DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 DBREAK + RSLC2 5 51 ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 RLGATE 1 9 10 RLDRAIN 2 5 20 RLSOURCE 3 7 4.
PAGE 8
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 SABER Electrical Model nom temp=25 deg c 100v Ultrafet REV Oct. 98 template huf75639 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is=1.4e-12, xti=4.7, cjo=33e-10,tt=6.1e-8, m=0.7) d..model dbreakmod = () d..model dplcapmod = (cjo=22e-10,is=1e-30,n=10,m=0.95, vj=1.0) m..model mmedmod = (type=_n,vto=3.5,kp=4.8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.97,kp=56.5,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.11,kp=0.
PAGE 9
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 Spice Thermal Model TH JUNCTION REV APRIL 1998 HUF75639 CTHERM1 TH 6 2.8e-3 CTHERM2 6 5 4.6e-3 CTHERM3 5 4 5.5e-3 CTHERM4 4 3 9.2e-3 CTHERM5 3 2 1.7e-2 CTHERM6 2 TL 4.3e-2 RTHERM1 RTHERM1 TH 6 5.0e-4 RTHERM2 6 5 1.5e-3 RTHERM3 5 4 2.0e-2 RTHERM4 4 3 9.0e-2 RTHERM5 3 2 1.9e-1 RTHERM6 2 TL 2.9e-1 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 Saber Thermal Model Saber thermal model HUF75639 template thermal_model th tl thermal_c th, tl { ctherm.
PAGE 10
HUF75639G3, HUF75639P3, HUF75639S3S, HUF75639S3 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.