Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsFETsIRLS640A, MOSFET

December 2013

IRLS640A

N-Channel Logic Level A-FET

200 V, 9.8 A, 180 mΩ

Description

IRLS640A — N-Channel Logic Level A-FET

IRLS640A Rev. C0

www.fairchildsemi.com

These N-Channel enhancement m

power field

transistors are produced using Fairchild’s

roprietary, planar, DMOS technology. This advanced

technology has been especially tailored to minimize

on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices

are well suited for high efficiency switching DC/DC

converters, switch mode power supplies, DC-AC

converters for uninterrupted power supply and motor

control.

Features

•

9.8 A, 200 V, R

DS(on)

= 180 mΩ @ V

= 5 V

•

Low Gate Charge (Typ. 40 nC)

•

Low Crss (Typ. 95 pF)

•

Fast Switching

•

100% Avalanche Tested

•

Improved dv/dt Capability

200

9.8

6.2

±20

4.0

0.32

- 55 to +150

300

Absolute Maximum Ratings

Characteristic

Drain-to-Source Voltage

Continuous Drain Current (T

=25℃)

Continuous Drain Current (T

=100℃)

Drain Current-Pulsed

①

Gate-to-Source Voltage

Single Pulsed Avalanche Energy

②

Avalanche Current

①

Repetitive Avalanche Energy

①

Peak Diode Recovery dv/dt

③

Total Power Dissipation (T

=25℃)

Linear Derating Factor

Operating Junction and

Storage Temperature Range

Maximum Lead Temp. for Soldering

Purposes, 1/8＂ from case for 5-seconds

Value Units

dv/dt

, T

STG

V/ns

W/℃

℃

Symbol

DSS

3.13

62.5

Thermal Resistance

Characteristic

Junction-to-Case

Junction-to-Ambient

θJC

θJA

Max. UnitsSymbol

Typ.

C/W

TO-220F

•

Logic-Level Gate Drive

Summary of content (8 pages)

PAGE 1
IRLS640A N-Channel Logic Level A-FET 200 V, 9.8 A, 180 mΩ Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode.
PAGE 2
Part Number IRLS640A Top Mark IRLS640A Package TO-220F Packing Method Tube Reel Size N/A Tape Width N/A Quantity 50 units Electrical Characteristics (TC=25℃ unless otherwise specified) Symbol Characteristic BVDSS Drain-Source Breakdown Voltage ΔBV/ΔTJ VGS(th) IGSS IDSS RDS(on) Min. Typ. Max. Units Breakdown Voltage Temp. Coeff.
PAGE 3
Fig 1. Output Characteristics Fig 2. Transfer Characteristics V GS 101 7.0 V 6.0 V 5.5 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V ID , Drain Current [A] ID , Drain Current [A] Top : @ Notes : 1. 250 µs Pulse Test 2. T = 25 oC 100 100 150 oC 100 25 oC @ Notes : 1. VGS = 0 V 2. VDS = 40 V 3. 250 µs Pulse Test - 55 oC C 10-1 101 10-1 101 0 2 4 6 8 10 VDS , Drain-Source Voltage [V] VGS , Gate-Source Voltage [V] Fig 3. On-Resistance vs. Drain Current Fig 4.
PAGE 4
(continued) Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature 2.0 RDS(on) , (Normalized) Drain-Source On-Resistance Drain-Source Breakdown Voltage BVDSS , (Normalized) 1.2 1.1 1.0 0.9 @ Notes : 1. VGS = 0 V 1.5 1.0 @ Notes : 1. VGS = 5 V 2. ID = 9 A 0.5 2. ID = 250 µA 0.8 -75 -50 -25 0 25 50 75 100 125 150 0.0 -75 175 -50 -5 2 TJ , Junction Temperature [oC] Fig 9. Max. Safe Operating Area 50 75 100 15 2 10 5 15 7 Fig 10. Max. Drain Current vs.
PAGE 5
IRLS640A — N-Channel Logic Level A-FET 50KΩ 200nF 12V VGS Same Type as DUT Qg 10V 300nF VDS VGS Qgs Qgd DUT IG = const. 3mA Charge Figure 12. Gate Charge Test Circuit & Waveform VDS RG RL VDS 90% VDD VGS VGS DUT V 10V GS 10% td(on) tr td(off) t on t off tf Figure 13. Resistive Switching Test Circuit & Waveforms VDS BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L BVDSS IAS ID RG V 10V GS GS VDD ID (t) VDS (t) VDD DUT tp Time tp Figure 14.
PAGE 6
+ VDS _ I SD L Driver RG VGS VGS ( Driver ) I SD ( DUT ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©1999 Fairchild Semiconductor Corporation IRLS640A Rev. C0 6 www.
PAGE 7
IRLS640A — N-Channel Logic Level A-FET Mechanical Dimensions Figure 16. TO220, Molded, 3-Lead, Full Pack, EIAJ SC91, Straight Lead Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.