LM555 Single Timer Features Description • • • • • The LM555 is a highly stable controller capable of producing accurate timing pulses. With a monostable operation, the delay is controlled by one external resistor and one capacitor. With astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor. High-Current Drive Capability: 200 mA Adjustable Duty Cycle Temperature Stability of 0.
LM555 — Single Timer Block Diagram R GND GND 1 Trigger Trigger 2 R Comp. Output Output Reset Reset 3 R 8 VCC Vcc 7 Discharge Discharge 6 Threshold Threshold 5 Control Control Threshold Voltage Voltage Discharging Tr. Discharging Transistor OutPut Stage F/F Comp. 4 VREF Vref Figure 1. Block Diagram Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device.
Values are at TA = 25°C, VCC = 5 ~ 15 V unless otherwise specified. Parameter Symbol Supply Voltage VCC Supply Current (Low Stable) (1) ICC Timing Error (Monostable) Initial Accuracy (2) ACCUR Drift with Temperature (3) Δt / ΔT Drift with Supply Voltage (3) Timing Error (Astable) InItial Accuracy (2) Drift with Temperature (3) Drift with Supply Voltage (3) Control Voltage Δt / ΔT Trigger Voltage 4.
Table 1 below is the basic operating table of 555 timer. Table 1. Basic Operating Table Reset (PIN 4) VTR (PIN 2) VTH (PIN 6) Discharging Transistor (PIN 7) Output (PIN 3) Low X X Low ON High < 1/3 VCC X High OFF High > 1/3 VCC > 2/3 VCC Low ON High > 1/3 VCC < 2/3 VCC Previous State When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage.
Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low, the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time.
LM555 — Single Timer Figure 8. Waveforms of Astable Operation An astable timer operation is achieved by adding resistor RB to Figure 2 and configuring as shown on Figure 6. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi-vibrator. When the timer output is high, its internal discharging transistor. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C.
LM555 — Single Timer The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows: RB C1 VC1(0-)=2Vcc/3 RD dv C1 1 C --------------- + -----------------------V =0 1 dt C1 R +R A B V C1 2 ( t ) = --- V 3 CC e (6) t - ------------------------------------( R A + R D )C1 ( 7) Since the duration of the timer output low state (tL) is the amount of time it takes for the VC1(t) to reach VCC/3, t L ------------------------------------- ( RA + RD )C1 1 2 --- V = ---V (
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 9. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. Figure 9. Waveforms of Frequency Divider Operation 4. Pulse Width Modulation The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators.
If the modulating signal is applied to the control terminal while the timer is connected for the astable operation, as in Figure 12, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated, which modulates the timer output according to the modulation signal applied to the control terminal.
LM555 — Single Timer In Figure 14, current source is created by PNP transistor Q1 and resistor R1, R2, and RE. V CC – V E = --------------------------( 12 ) C R E Here, V E is R 2 V = V + ---------------------- V ( 13 ) E BE R + R CC 1 2 For example, if VCC = 15 V, RE = 20 kΩ, R1 = 5 kΩ, R2 = 10 kΩ, and VBE = 0.7 V, VE=0.7 V+10 V=10.7 V, and IC=(15-10.7) / 20 k=0.215 mA.
LM555 — Single Timer Physical Dimensions 8-DIP .400 10.15 .373 9.46 [ A ] .036 [0.9 TYP] (.092) [Ø2.337] (.032) [R0.813] PIN #1 .250±.005 [6.35±0.13] PIN #1 B TOP VIEW OPTION 1 TOP VIEW OPTION 2 [ ] .070 1.78 .045 1.14 .310±.010 [7.87±0.25] .130±.005 [3.3±0.13] .210 MAX [5.33] 7° TYP 7° TYP C .015 MIN [0.38] .140 3.55 .125 3.17 .021 0.53 .015 0.37 [ ] .001[.025] C .300 [7.62] [ ] .100 [2.54] .430 MAX [10.92] .060 MAX [1.52] NOTES: A.
LM555 — Single Timer Physical Dimensions (continued) 8-SOIC Figure 17. 8-Lead, SOIC,JEDEC MS-012, 150" NARROW BODY Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
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