Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Gate and converter - configurable Asymmetric SC 70 6

December 2010

NC7SV57 • NC7SV58 • Rev. 1.0.4

NC7SV57 / NC7SV58 — TinyLogic

ULP-A Universal Configuration Two-Input Logic Gates

NC7SV57 / NC7SV58

TinyLogic

ULP-A Universal Configurable Two-Input

Logic Gates

Features

 0.9V to 3.6V V

Supply Operation

 3.6V Over-Voltage Tolerant I/Os at V

from 0.9V to 3.6V

 Extremely High Speed tPD

- 2.5ns: Typical for 2.7V to 3.6V V

- 3.1ns: Typical for 2.3V to 2.7V V

- 4.0ns: Typical for 1.65V to 1.95V V

- 6.0ns: Typical for 1.4V to 1.6V V

- 8.0ns: Typical for 1.1V to 1.3V V

- 23.0ns: Typical for 0.9V V

 Power-Off High-Impedance Inputs and Outputs

 High Static Drive (I

)

- ±24mA at 3.00V V

- ±18mA at 2.30V V

- ±6mA at 1.65V V

- ±4mA at 1.4V V

- ±2mA at 1.1V V

- ±0.1mA at 0.9V V

 Proprietary Quiet Series™ Noise/EMI Reduction

 Ultra-Small MicroPak™ Package

 Ultra-Low Dynamic Power

Description

The NC7SV57 and NC7SV58 are universal configurable

two-input logic gates from Fairchild’s Ultra-Low Power

(ULP-A) series of TinyLogic

. ULP-A is ideal for

applications that require extreme high-speed, high

drive, and low power. This product is designed for a

wide low-voltage operating range (0.9V to 3.6V V

)

and applications that require more drive and speed than

the TinyLogic

ULP series, but still offer best-in-class,

low-power operation.

Each device is capable of being configured for 1 of 5

unique two-input logic functions. Any possible two-input

combinatorial logic function can be implemented, as

shown in the Function Selection Table. Device

functionality is selected by how the device is wired at

the board level. Figures 1 through 10 illustrate how to

connect the NC7SV57 and NC7SV58, respectively, for

the desired logic function. All inputs have been

implemented with hysteresis.

The NC7SV57 and NC7SV58 are uniquely designed for

optimized power and speed and are fabricated with an

advanced CMOS technology to achieve high-speed

operation while maintaining low CMOS power

dissipation.

Ordering Information

Part Number Top Mark Package Packing Method

NC7SV57P6X V57 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide

3000 Units on

Tape & Reel

NC7SV57L6X H3 6-Lead Micropak™, 1.0mm Wide

5000 Units on

Tape & Reel

NC7SV57FHX H3 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

NC7SV58P6X V58 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide

3000 Units on

Tape & Reel

NC7SV58L6X H4 6-Lead Micropak™, 1.0mm Wide

5000 Units on

Tape & Reel

NC7SV58FHX H4 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

Summary of content (14 pages)

PAGE 1
NC7SV57 / NC7SV58 TinyLogic® ULP-A Universal Configurable Two-Input Logic Gates Features Description 0.9V to 3.6V VCC Supply Operation Extremely High Speed tPD - 2.5ns: Typical for 2.7V to 3.6V VCC - 3.1ns: Typical for 2.3V to 2.7V VCC - 4.0ns: Typical for 1.65V to 1.95V VCC - 6.0ns: Typical for 1.4V to 1.6V VCC - 8.0ns: Typical for 1.1V to 1.3V VCC - 23.0ns: Typical for 0.
PAGE 2
Figure 1. Battery Life vs. VCC Supply Voltage Notes: ® 1. TinyLogic ULP and ULP-A with up to 50% less power consumption can extend your battery life significantly. Battery Life = (Vbattery•Ibattery•.9)/(Pdevice)/24hrs/day 2 where Pdevice = (ICC • VCC) + (CPD + CL) • VCC • f. 2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at 10MHz, with CL = 15pF load. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.
PAGE 3
Figure 2. SC70 (Top View) Figure 3. MicroPak™ (Top Through View) Figure 4. Pin 1 Orientation Notes: 3. AAA represents product code top mark (see Ordering Information). 4. Orientation of top mark determines pin one location. 5. Reading the top mark left to right, pin one is the lower left pin. Pin Definitions Pin # SC70 Pin # MicroPak™ Name 1 1 I1 2 2 GND 3 3 I0 Data Input 4 4 Y Output 5 5 VCC 6 6 I2 © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.
PAGE 4
Inputs NC7SV57 NC7SV58 I2 I1 I0 Y = (I0) • (I2) + (I1) • (I2) Y = (I0) • (I2) + (I1) • (I2) L L L H L L L H L H L H L H L L H H L H H L L L H H L H L H H H L H L H H H H L H = HIGH Logic Level L = LOW Logic Level Function Selection Table 2-Input Logic Function Device Selection Connection Configuration 2-Input AND NC7SV57 Figure 5 2-Input AND with Inverted Input NC7SV58 Figure 11, Figure 12 2-Input AND with Both Inputs Inverted NC7SV57 Figure 8 2-I
PAGE 5
Figure 5 that can diagrams for a implementation is next to the board-level physical implementation of how the pins of the function should be connected. through Figure 9 show the logical functions be implemented using the NC7SV57. The show the DeMorgan’s equivalent logic duals given two-input function. The logical Figure 5. Figure 7. 2-Input AND Gate Figure 6. 2-Input NAND with Inverted B Input Figure 9. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.
PAGE 6
implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure 10 through Figure 14 show the logical functions that can be implemented using the NC7SV58. The diagrams show the DeMorgan’s equivalent logic duals for a given two-input function. The logical Figure 10. Figure 12. 2-Input NAND Gate Figure 11. 2-Input AND Gate with Inverted A Input 2-Input AND with Inverted B Input Figure 14.
PAGE 7
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
PAGE 8
Symbol Parameter VCC Conditions 0.90 VP VN VH Positive Threshold Voltage Negative Threshold Voltage TA=-40 to 85°C Min. Max. Min. Max. 0.30 0.70 0.30 0.70 1.10 0.40 1.00 0.40 1.00 1.40 0.50 1.40 0.50 1.40 1.65 0.70 1.50 0.70 1.50 2.30 1.00 1.80 1.00 1.80 2.70 1.30 2.20 1.30 2.20 0.90 0.10 0.60 0.10 0.60 1.10 0.15 0.70 0.15 0.70 1.40 0.20 0.80 0.20 0.80 1.65 0.25 0.90 0.25 0.90 2.30 0.40 1.15 0.40 1.15 2.70 0.60 1.50 0.60 1.50 0.90 0.
PAGE 9
Symbol Parameter VCC TA=25°C Conditions Min. Max. 0.90 LOW Level Output Voltage 0.1 0.1 0.2 0.2 0.2 0.2 2.30 ≤ VCC ≤ 2.70 0.2 0.2 2.70 ≤ VCC ≤ 3.60 0.2 0.2 1.10 ≤ VCC ≤ 1.30 IOL=2mA .25 x VCC .25 x VCC 1.40 ≤ VCC ≤ 1.60 IOL=4mA .25 x VCC .25 x VCC 1.65 ≤ VCC ≤ 1.95 IOL=6mA 0.3 0.3 0.4 0.4 0.4 0.4 2.70 ≤ VCC ≤ 3.60 2.30 ≤ VCC ≤ 2.70 2.70 ≤ VCC ≤ 3.60 2.70 ≤ VCC ≤ 3.60 IIN 0.90 to 3.60 IOFF Power Off Leakage Current ICC Quiescent Supply Current 0.1 1.10 ≤ VCC ≤ 1.
PAGE 10
Figure 15. AC Test Circuit Figure 16. AC Waveforms VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.10V 1.2V ± 0.10V 0.9V Vmi 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates AC Loadings and Waveforms www.fairchildsemi.
PAGE 11
SYMM C L 2.00±0.20 0.65 A 0.50 MIN 6 4 B PIN ONE 1.25±0.10 1 1.90 3 0.30 0.15 (0.25) 0.40 MIN 0.10 0.65 A B 1.30 LAND PATTERN RECOMMENDATION 1.30 1.00 0.80 SEE DETAIL A 1.10 0.80 0.10 C 0.10 0.00 C 2.10±0.30 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE (R0.10) 0.25 0.10 0.20 A) THIS PACKAGE CONFORMS TO EIAJ SC-88, 1996. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. D) DRAWING FILENAME: MKT-MAA06AREV6 30° 0° 0.46 0.
PAGE 12
2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 6X 0.15 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X Notes: BOTTOM VIEW (0.13) 4X DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.
PAGE 13
0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 0.35 6 5 0.60 4 (0.08) 4X BOTTOM VIEW 0.10 .05 C C B A 0.40 0.30 NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS.
PAGE 14
NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 www.fairchildsemi.