Datasheet

ManualsBrandsFAIRCHILD SEMICONDUCTOR ManualsLogic ICsLogic IC - Gate and inverter NOR gate 7SZ SC 70 5

December 2010

NC7SZ02 • Rev. 1.0.5

NC7SZ02 — TinyLogic

UHS Two-Input NOR Gate

NC7SZ02

TinyLogic

UHS Two-Input NOR Gate

Features

 Ultra-High Speed: t

2.4ns (Typical) into 50pF at

5V V

 High Output Drive: ±24mA at 3V V

 Broad V

Operating Range: 1.65V to 5.5V

 Matches Performance of LCX Operated at 3.3V V

 Power Down High-Impedance Inputs/Outputs

 Over-Voltage Tolerance Inputs Facilitate 5V to 3V

Translation

 Proprietary Noise/EMI Reduction Circuitry

 Ultra-Small MicroPak™ Packages

 Space-Saving SOT23 and SC70 Packages

Description

The NC7SZ02 is a single two-input NOR gate from

Fairchild’s Ultra-High Speed (UHS) series of

TinyLogic

. The device is fabricated with advanced

CMOS technology to achieve ultra-high speed with high

output drive while maintaining low static power

dissipation over a broad V

operating range. The

device is specified to operate over the 1.65V to 5.5V

operating range. The inputs and output are high-

impedance when V

is 0V. Inputs tolerate voltages up

to 6V, independent of V

operating voltage.

Ordering Information

Part Number Top Mark Package Packing Method

NC7SZ02M5X 7Z02 5-Lead SOT23, JEDEC MO-178 1.6mm 3000 Units on Tape & Reel

NC7SZ02P5X Z02 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel

NC7SZ02L6X JJ 6-Lead MicroPak™, 1.00mm Wide 5000 Units on Tape & Reel

NC7SZ02FHX JJ 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel

Summary of content (10 pages)

PAGE 1
NC7SZ02 TinyLogic® UHS Two-Input NOR Gate Features Description Ultra-High Speed: tPD 2.4ns (Typical) into 50pF at 5V VCC High Output Drive: ±24mA at 3V VCC The NC7SZ02 is a single two-input NOR gate from Fairchild’s Ultra-High Speed (UHS) series of ® TinyLogic . The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive while maintaining low static power dissipation over a broad VCC operating range.
PAGE 2
NC7SZ02 — TinyLogic® UHS Two-Input NOR Gate Connection Diagrams IEEE/IEC Figure 1. Logic Symbol Pin Configurations Figure 2. SC70 and SOT23 (Top View) Figure 3.
PAGE 3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN VOUT Parameter Min. Max. Unit Supply Voltage -0.5 6.0 V DC Input Voltage -0.5 6.
PAGE 4
Symbol Parameter VCC TA=25°C Conditions Min. Typ. TA=-40 to +85°C Max. Min. VIH HIGH Level Input Voltage 1.65 to 1.95 0.75VCC 0.75VCC 2.30 to 5.50 0.70VCC 0.70VCC VIL LOW Level Input Voltage 1.65 to 1.95 0.25VCC 0.25VCC 2.30 to 5.50 0.30VCC 0.30VCC 1.65 1.55 1.65 1.55 1.80 1.70 1.80 1.70 2.20 2.30 2.20 2.90 3.00 2.90 2.30 VIN=VIL IOH=-100µA 3.00 VOH HIGH Level Output Voltage 4.50 4.40 4.50 4.40 1.65 IOH=-4mA 1.29 1.52 1.29 2.30 IOH=-8mA 1.90 2.15 1.
PAGE 5
Symbol Parameter VCC TA=25°C Conditions 1.65 1.80 2.50 ± 0.20 tPLH, tPHL Propagation Delay CL=15pF, RL=1MΩ 3.30 ± 0.30 TA=-40 to +85°C Min. Typ. Max. Min. Max. 2.0 5.3 11.5 2.0 12.0 2.0 4.4 9.5 2.0 10.0 0.8 2.9 6.5 0.8 7.0 0.5 2.3 4.5 0.5 4.7 5.00 ± 0.50 0.5 1.9 3.9 0.5 4.1 3.30 ± 0.30 CL=50pF, 5.00 ± 0.50 RL=500Ω 1.5 2.9 5.0 1.5 5.2 0.8 2.4 4.3 0.8 4.5 CIN Input Capacitance 0 4 CPD Power Dissipation Capacitance(2) 3.30 23 5.
PAGE 6
NC7SZ02 — TinyLogic® UHS Two-Input NOR Gate Physical Dimensions 3.00 2.80 5 SYMM CL 0.95 0.95 A 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 0.20 1.90 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8° 0° 0.55 0.35 SEATING PLANE 0.
PAGE 7
NC7SZ02 — TinyLogic® UHS Two-Input NOR Gate Physical Dimensions Figure 8. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision.
PAGE 8
NC7SZ02 — TinyLogic® UHS Two-Input NOR Gate Physical Dimensions 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X BOTTOM VIEW Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2.
PAGE 9
NC7SZ02 — TinyLogic® UHS Two-Input NOR Gate Physical Dimensions 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A.
PAGE 10
NC7SZ02 — TinyLogic® UHS Two-Input NOR Gate © 1996 Fairchild Semiconductor Corporation NC7SZ02 • Rev. 1.0.5 www.fairchildsemi.