Datasheet

June 1997
NDP6030PL / NDB6030PL
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
________________________________________________________________________________
Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Symbol Parameter NDP6030PL NDB6030PL Units
V
DSS
Drain-Source Voltage -30 V
V
GSS
Gate-Source Voltage - Continuous ±16 V
I
D
Drain Current - Continuous -30 A
- Pulsed -90
P
D
Total Power Dissipation @ T
C
= 25°C
75 W
Derate above 25°C 0.5
T
J
,T
STG
Operating and Storage Temperature Range -65 to 175 °C
T
L
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
275 °C
T
J
,T
STG
Operating and Storage Temperature Range -65 to 175 °C
THERMAL CHARACTERISTICS
R
θ
JC
Thermal Resistance, Junction-to-Case 2 °C/W
R
θJA
Thermal Resistance, Junction-to-Ambient 62.5 °C/W
NDP6030PL Rev.B1
-30 A, -30 V. R
DS(ON)
= 0.042 Ω @ V
GS
= -4.5 V
R
DS(ON)
= 0.025 Ω @ V
GS
= -10 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
High density cell design for extremely low R
DS(ON)
.
175°C maximum junction temperature rating.
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance.
These devices are particularly suited for low voltage
applications such as DC/DC converters and high efficiency
switching circuits where fast switching, low in-line power loss,
and resistance to transients are needed.
S
D
G
© 1997 Fairchild Semiconductor Corporation