Datasheet

April 1996
NDP6060L / NDB6060L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
________________________________________________________________________________
Absolute Maximum Ratings T
C
= 25°C unless otherwise noted
Symbol Parameter NDP6060L NDB6060L Units
V
DSS
Drain-Source Voltage 60 V
V
DGR
Drain-Gate Voltage (R
GS
< 1 MΩ)
60 V
V
GSS
Gate-Source Voltage - Continuous ± 16 V
- Nonrepetitive (t
P
< 50 µs)
± 25
I
D
Drain Current - Continuous 48 A
- Pulsed 144
P
D
Total Power Dissipation @ T
C
= 25°C 100 W
Derate above 25°C 0.67 W/°C
T
J
,T
STG
Operating and Storage Temperature -65 to 175 °C
T
L
Maximum lead temperature for soldering
purposes, 1/8" from case for 5 seconds
275 °C
NDP6060L Rev. D / NDB6060L Rev. E
These logic level N-Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulses in the
avalanche and commutation modes. These devices are
particularly suited for low voltage applications such as
automotive, DC/DC converters, PWM motor controls,
and other battery powered circuits where fast switching,
low in-line power loss, and resistance to transients are
needed.
48A, 60V. R
DS(ON)
= 0.025Ω @ V
GS
= 5V.
Low drive requirements allowing operation directly from logic
drivers. V
GS(TH)
< 2.0V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged internal source-drain diode can eliminate the need
for an external Zener diode transient suppressor.
175°C maximum junction temperature rating.
High density cell design for extremely low R
DS(ON)
.
TO-220 and TO-263 (D
2
PAK) package for both through hole
and surface mount applications.
S
D
G
© 1997 Fairchild Semiconductor Corporation