Datasheet

August 1996
NDT014L
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
_________________________________________________________________________________
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter NDT014L Units
V
DSS
Drain-Source Voltage 60 V
V
GSS
Gate-Source Voltage ± 20 V
I
D
Drain Current - Continuous (Note 1a) ± 2.8 A
- Pulsed ± 10
P
D
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b) 1.3
(Note 1c)
1.1
T
J
,T
STG
Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
NDT014L Rev.D
2.8 A, 60 V. R
DS(ON)
= 0.2 @ V
GS
= 4.5 V
R
DS(ON)
= 0.16 @ V
GS
= 10 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
These N-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology.This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation
modes.Thesedevices are particularly suited for low voltage
applications such as DC motor control and DC/DC
conversion where fast switching, low in-line power loss, and
resistance to transients are needed.
D
D S
G
D
S
G
© 1997 Fairchild Semiconductor Corporation

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