Datasheet

May 1998
NDT3055
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless otherwise noted
Symbol Parameter NDT3055 Units
V
DSS
Drain-Source Voltage 60 V
V
GSS
Gate-Source Voltage - Continuous ±20 V
I
D
Maximum Drain Current - Continuous (Note 1a) 4 A
- Pulsed 25
P
D
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
1.3
(Note 1c)
1.1
T
J
,T
STG
Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT3055 Rev.B
4 A, 60 V. R
DS(ON)
= 0.100 Ω @ V
GS
= 10 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely used
surface mount package.
SOIC-16
SuperSOT
TM
-3
SuperSOT
TM
-8
SO-8
SOT-223
SuperSOT
TM
-6
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for
low voltage applications such as DC motor control and
DC/DC conversion where fast switching, low in-line
power loss, and resistance to transients are needed.
G
D
S
D
SOT-223
D
D S
G
G
D
S
SOT-223*
(J23Z)
D
S
G
© 1998 Fairchild Semiconductor Corporation