Datasheet

June 1996
NDT454P
P-Channel Enhancement Mode Field Effect Transistor
General Description Features
____________________________________________________________________________________________
Absolute Maximum Ratings T
A
= 25°C unless otherwise noted
Symbol Parameter NDT454P Units
V
DSS
Drain-Source Voltage -30 V
V
GSS
Gate-Source Voltage ±20 V
I
D
Drain Current - Continuous (Note 1a) ±5.9 A
- Pulsed ±15
P
D
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
1.3
(Note 1c)
1.1
T
J
,T
STG
Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT454P Rev. D2
Power SOT P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
-5.9A, -30V. R
DS(ON)
= 0.05Ω @ V
GS
= -10V
R
DS(ON)
= 0.07Ω @ V
GS
= -6V
R
DS(ON)
= 0.09Ω @ V
GS
= -4.5V.
High density cell design for extremely low R
DS(ON).
High power and current handling capability in a widely used
surface mount package.
D
D S
G
D
S
G
© 1997 Fairchild Semiconductor Corporation