Data Sheet

FSC-BT1006A Datasheet
Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com
-15-
When the battery is fully charged, the charger enters standby mode, and battery charging stops. The battery
voltageon the VBAT_SENSE pin is monitored, and when it drops below a threshold set at V
hyst
below the final
chargingvoltage, V
float
, the charger re-enters fast charge mode.
Error Mode
The charger enters the error mode if the voltage on the VCC_CHG pin is too low to operate the charger
correctly(VBAT_SENSE is greater than VCC_CHG - 50mV (typical)).
In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation.
4.1.2.2 Battery Charger Trimming and Calibration
The battery charger default trim values are written by Feasycom into non-volatile memory when each IC is
produced. Feasycom provides various PS Keys for overriding the default trims.
4.1.2.3 On-chip application Battery Charger Control
The on-chip applicationcharger code has overall supervisory control of the battery charger and is responsible for:
Responding to charger power connection/disconnection events
Monitoring the temperature of the battery
Monitoring the temperature of the die to protect against silicon damage
Monitoring the time spent in the various charge states
Enabling/disabling the charger circuitry based on the monitored information
Driving the user visible charger status LED(s)
4.1.2.4 Battery Charger Firmware and PS Keys
The battery charger firmware sets up the charger hardware based on the PS Key settings and call traps from the VM
charger code. It also performs the initial analogue trimming. Settings for the charger current depend on the battery
capacity and type, which are set by the user in the PS Keys.
4.2 Reset
FSC-BT1006A is reset from several sources:
Power-on reset
USB charger attach reset
Software configured watchdog timer
At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.
NOTE: Reset can also be triggered by a UART break symbol if:
Host interface is any UART transport
And