Data Sheet

FSC-BT1006A Datasheet

Shenzhen Feasycom Technology Co.,Ltdwww.feasycom.com

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Module Host

TX RX

GND

CTS

RTS

CTS

Figure 5: UART Connection

The UART interface resets FSC-BT1006A on reception of a break signal. A break is identified by a continuous logic

low (0V) on the UART_RX terminal, as belowpicture shows. If t BRK is longer than the value defined by the

PSKEY_HOSTIO_ UART _RESET_TIMEOUT, a reset occurs. This feature enables a host to initialise the system toa

known state. Also, FSC-BT1006A can issue a break character for waking the host.

Figure 6: Break Signal

The UART interface is tristate while FSC-BT1006A is being held in reset. This enables the user to connect

otherdevices onto the physical UART bus. The restriction with this method is that any devices connected to this bus

musttristate when FSC-BT1006A reset is de-asserted and the firmware begins to run.

4.6.2 I

C Interface

FSC-BT1006A includes a configurable I

C interface.

C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between

devices. The I

C standard is a true multi-master bus including collision detection and arbitration that prevents data

corruption if two or more masters attempt to control the bus simultaneously.

Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis.

Each data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An

acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the

SDA line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A

transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the

following figure for more details about I

C Bus Timing.