Data Sheet

FSC-BT691 Datasheet
Shenzhen Feasycom Technology Co.,Ltd www.feasycom.com
-7-
ADC1
SWDCLK
I
Alternative Function: Analog to Digital Converter input 1.
Alternative Function: JTAG clock signal (by default).
11,12
NC
NC (Do not connect to any pin)
15
PIO7
ADC3
I/O
I
Programmable input/output line
Alternative Function: Analog to Digital Converter input 3.
16
NC
NC (Do not connect to any pin)
17
PIO5
I/O
Programmable input/output line
18
PIO11
I/O
Programmable input/output line
19
GND
Vss
Power Ground
20
RF
O
RF signal output .
4. PHYSICAL INTERFACE
4.1 Power Supply
The transient response of the regulator is important. If the power rails of the module are supplied from an external
voltage source, the transient response of any regulator used should be 20μs or less. It is essential that the power rail
recovers quickly.
4.2 Reset
Comprises a reset (RST) pad which is active high. It contains an RC filter with a resistor of 65 kΩ and a capacitor of 3.5
pF to suppress spikes. It also contains a 25 kΩ pull-down resistor. This pad should be driven externally by a field-effect
transistor (FET) or a single button connected to VBAT. The typical latency of the RST pad is in the range of 2 μs.
4.3 General Purpose Analog IO
The FSC-BT691 is equipped with a high-speed ultra-low-power 10-bit general purpose Analog-to-Digital
Converter (GPADC). It can operate in unipolar (single ended) mode as well as in bipolar (differential) mode. The
ADC has its own voltage regulator (LDO) of 0.9 V, which represents the full-scale reference voltage.
10-bit dynamic ADC with 125 ns typical conversion time
Maximum sampling rate 1 Msample/s
128x averaging; conversion time 1 ms, up to 11b ENOB
Ultra-low power (20 uA typical supply current at 100 ksample/s)
Two single-ended or two differential external input channels (GPIOs)
Battery, DCDC outputs, and the internal VDD monitoring channels
Chopper function
Offset adjust
Common-mode input level adjust
Configurable attenuator: 1x, 2x, 3x and 4x
Input shifter