FSC-BT806 Datasheet FSC-BT806A 5.0 Dual Mode Bluetooth Module Datasheet Version 1.2 Shenzhen Feasycom Technology Co.,Ltd -1- www.feasycom.
FSC-BT806 Datasheet Copyright © 2013-2019 Feasycom Technology. All Rights Reserved. Feasycom Technology reserves the right to make corrections, modifications, and other changes to its products, documentation and services at anytime. Customers should obtain the newest relevant information before placing orders. To minimize customer product risks, customers should provide adequate design and operating safeguards.
FSC-BT806 Datasheet Contents 1. INTRODUCTION ............................................................................................................................................................... 5 2. GENERAL SPECIFICATION ................................................................................................................................................. 7 3. HARDWARE SPECIFICATION ...................................................................................................
FSC-BT806 Datasheet 5.4.1 Analogue to Digital Converter .................................................................................................................................. 40 5.4.1 Digital to Analogue Converter .................................................................................................................................. 40 5.5 AUXILIARY ADC .................................................................................................................................
FSC-BT806 Datasheet 1. INTRODUCTION Overview Music Enhancements: SBC,MP3,AAC and AAC+,Faststream codec,atpX,5-band EQ,3D stereo FSC-BT806A is a Bluetooth 5.0 dual-mode module. It provides a Bluetooth Low Energy fully compliant system for audio and data communication with Feasycom stack. FSC-BT806A integrates an ultra-low-power DSP and application processor with embedded flash memory, a high-performance stereo codec, a power management subsystem, I2S, LED drivers and ADC I/O in a SOC IC.
FSC-BT806 Datasheet Module picture as below showing Figure 1: FSC-BT806A Picture Shenzhen Feasycom Technology Co.,Ltd -6- www.feasycom.
FSC-BT806 Datasheet 2. General Specification Table 1: General Specifications Categories Features Implementation On-board chip CSR8670 V5.0 Dual-mode Bluetooth low energy radio Software complies with the Bluetooth Core v5.0 Specification Bluetooth Low energy Support for Bluetooth basic rate / EDR and low energy Connections 3 Bluetooth low energy connections at the same time as basic rate A2DP Wireless Specification Frequency 2.402 - 2.
FSC-BT806 Datasheet Simultaneous BR/EDR and BLE support Maximum Connections BR/EDR up to 7 active slaves Bluetooth Low Energy 1 connection as peripheral , up to 5 connections as central Via UART FW upgrade USB SPI Supply Voltage Supply VDD_IO: 1.7 ~ 3.6V ; VBAT_IN: 2.8V ~ 4.3V Max Peak Current(TX Power @ +10dBm TX): 85mA Power Consumption Standby Doze (Wait event) - <1mA (TBD) Deep Sleep - ~300uA(TBD) Physical Environmental Miscellaneous Dimensions 13mm(W) X 26.9mm(L) X 2.
FSC-BT806 Datasheet GND AIO0 AIO1 I2S_CLK I2S_IN I2S_OUT I2S_WS RESET SPI_CSB SPI_MOSI SPI_MISO SPI_CLK BT_TX BT_RX BT_CTS BT_RTS LED0 LED1 LED2 PIO0 PIO1 GND EXT_ANT GND SPK_LP SPK_LN SPK_RP SPK_RN PIO4 PIO5 PIO6 PIO7 PIO14 PIO15 VDD_USB/3.3V_OUT MIC_L_BIAS MIC_LN MIC_LP MIC_R_BIAS GND PIO2 PIO3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 MIC_RN MIC_RP VCC_CHG USB_DN USB_DP VDD_IO 1.
FSC-BT806 Datasheet 7 I2S_WS I/O 8 RESET I 9 SPI_CSB I/O Chip select for SPI, active low.(Debug) 10 SPI_MOSI I/O SPI data input. (Debug) 11 SPI_MISO I/O SPI data output. (Debug) 12 SPI_CLK I/O SPI clock. (Debug) 13 BT_TX I/O UART Data output Alternative Function: Programmable input/output line Note6 14 BT_RX I/O UART Data input Alternative Function: Programmable input/output line Note 6 15 BT_CTS I/O UART clear to send, active low.
FSC-BT806 Datasheet 41 MIC_RN I Microphone input negative, right 42 MIC_R_BIAS O Microphone R bias 43 MIC_LP I Microphone input positive, left 44 MIC_LN I Microphone input negative, left 45 MIC_L_BIAS O Microphone L bias 46 SPK_RN O Speaker output negative, right 47 SPK_RP O Speaker output positive, right 48 SPK_LN O Speaker output negative, left 49 SPK_LP O Speaker output positive, left 50 GND Vss Power Ground 51 EXT_ANT RF Bluetooth 50Ω transmitter output /recei
FSC-BT806 Datasheet 4. PHYSICAL INTERFACE 4.1 Power Management 4.1.1 Power Supply The transient response of the regulator is important. If the power rails of the module are supplied from an external voltage source, the transient response of any regulator used should be 20μs or less. It is essential that the power rail recovers quickly. 4.1.2 Battery Charger 4.1.2.1 Battery Charger Hardware Operating Modes The default mode for the FSC-BT806A battery charger is OFF.
FSC-BT806 Datasheet Figure 4: Battery Charger Mode-to-Mode Transition Diagram Disabled Mode In the disabled mode the battery charger is fully disabled and draws no active current on any of its terminals. Trickle Charge Mode In the trickle charge mode, when the voltage on VBAT_SENSE is lower than the Vfast threshold, a current of approximately 10% of the fast charge current, Ifast, is sourced from the VBAT_IN pin.
FSC-BT806 Datasheet Error Mode The charger enters the error mode if the voltage on the VCC_CHG pin is too low to operate the charger correctly (VBAT_SENSE is greater than VCC_CHG - 50mV (typical)). In this mode, charging is stopped. The battery charger does not require a reset to resume normal operation. 4.1.2.2 Battery Charger Trimming and Calibration The battery charger default trim values are written into internal flash when each IC is characterised. Please contact Feasycom regarding to PS keys. 4.1.
FSC-BT806 Datasheet The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be applied for a period greater than 5ms. At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state. The PIOs have weak pull-ups. 4.2.1 Digital Pin States on Reset This table shows the pin states of FSC-BT806A on reset.
FSC-BT806 Datasheet Note: The reset protection is cleared after typically 2s (1.6s min to 2.4s max). If RST# is held low for >2.4s FSC-BT806A turns off. A rising edge on VREGENABLE or VCC_CHG is required to power on FSC-BT806A. 4.3 General Purpose Analog IO FSC-BT806A has 1 general-purpose analogue interface pins, AIO1, for accessing internal circuitry and control signals. Auxiliary functions available on the analogue interface include a 10-bit ADC and a 10-bit DAC.
FSC-BT806 Datasheet This is a standard UART interface for communicating with other serial devices. The UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. When the module is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. This module output is at 3.
FSC-BT806 Datasheet The UART interface is tristate while FSC-BT806A is being held in reset. This enables the user to connect other devices onto the physical UART bus. The restriction with this method is that any devices connected to this bus must tristate when FSC-BT806A reset is de-asserted and the firmware begins to run. 4.6.2 I2C Interface FSC-BT806A includes a configurable I2C interface.
FSC-BT806 Datasheet USB suspend modes and Bluetooth low-power modes: Global suspend Selective suspend, includes remote wake Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend Suspend mode current draw PIO status in suspend mode Resume, detach and wake PIOs Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration USB termination when interface is not in use Internal modules, ce
FSC-BT806 Datasheet Note: The LED current adds to the overall current. Conservative LED selection extends battery life. 4.8 Audio Interfaces The audio interface circuit consists of: Stereo/dual-mono audio codec Dual analogue audio inputs Dual analogue audio outputs 2 digital MEMS microphone inputs A configurable PCM, I²S or SPDIF interface Figure 9: Audio Interface The interface for the digital audio bus shares the same pins as the PCM codec interface described.
FSC-BT806 Datasheet 4.8.
FSC-BT806 Datasheet Audio Codec Block Diagram Figure 10: Audio Codec Input and Output Stages FSC-BT806A audio codec uses a fully differential architecture in the analogue signal path, which results in low noise sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a dual power supply, VDD_AUDIO(internal) for the audio circuits and VDD_AUDIO_DRV (internal)for the audio driver circuits.
FSC-BT806 Datasheet ADC Sample Rate Selection Each ADC supports the following pre-defined sample rates, although other rates are programmable, e.g. 40kHz: 8kHz 11.025kHz 16kHz 22.050kHz 24kHz 32kHz 44.
FSC-BT806 Datasheet Table 7: ADC Audio Input Gain Rate Digital Gain Selection Value ADC Digital Gain Setting(dB) Digital Gain Selection Value ADC Digital Gain Setting(dB) 0 0 8 -24 1 3.5 9 -20.5 2 6 10 -18 3 9.5 11 -14.5 4 12 12 -12 5 15.5 13 -8.5 6 18 14 -6 7 21.5 15 -2.5 ADC Digital IIR Filter The ADC contains 2 integrated anti-aliasing filters: A long IIR filter suitable for music (>44.1kHz) G.
FSC-BT806 Datasheet DAC Digital Gain A digital gain stage inside the DAC varies from -24dB to 21.5dB, see following table. There is also a fine gain interface with a 9-bit gain setting enabling gain changes in 1/32 steps, for more information contact CSR. The overall gain control of the DAC is controlled by the firmware. Its setting is a combined function of the digital and analogue amplifier settings.
FSC-BT806 Datasheet IEC 60958 Interface The IEC 60958 interface is a digital audio interface that uses bi-phase coding to minimise the DC content of the transmitted signal and enables the receiver to decode the clock information from the transmitted signal. The IEC 60958 specification is based on the 2 industry standards: AES3 (also known as AES/EBU) Sony and Philips interface specification SPDIF The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4.
FSC-BT806 Datasheet Microphone Input FSC-BT806A contains an independent low-noise microphone bias generator. The microphone bias generator is recommended for biasing electret condensor microphones. Figure 9.6 shows a biasing circuit for microphones with a sensitivity between about -40 to -60dB (0dB = 1V/Pa). Where: The microphone bias generator derives its power from VBAT or 3V3_USB and requires no capacitor on its output. The microphone bias generator maintains regulation within the limits 70uA to 2.
FSC-BT806 Datasheet 1.8V or 2.6V Tolerance 90% to 110% Output current: 70uA to 2.8mA No load capacitor required Digital Microphone Inputs FSC-BT806A interfaces to 2 digital MEMS microphones. shows that 4 of the inputs have dedicated codec channels and 2 are multiplexed with the high-quality ADC channels. Clock lines shared between 2 microphone outputs, linked to any even-numbered PIO pin as determinedby the firmware.
FSC-BT806 Datasheet Figure 16: Single-ended Input 4.8.3 Output Stage The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling frequency to bit stream, which is fed into the analogue output circuitry. The analogue output circuit comprises a DAC, a buffer with gain-setting, a low-pass filter and a class AB output stage amplifier.
FSC-BT806 Datasheet PCM interface master, generating PCM_SYNC and PCM_CLK. PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK. Various clock formats including: Long Frame Sync Short Frame Sync GCI timing environments 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats. Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC.
FSC-BT806 Datasheet Short Frame Sync Figure 21: Short Frame Sync (shown with 16-bit Sample) Multi-slot Operation Figure 22: Multi Slot Operation with 2 Slots and 8-bit Companded Samples GCI Interface Figure 23: GCI Interface Shenzhen Feasycom Technology Co., Ltd -31- www.feasycom.
FSC-BT806 Datasheet Slots and Sample Formats FSC-BT806A receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are either 8 or 16 clock cycles: 8 clock cycles for 8-bit sample formats. 16 clocks cycles for 8-bit, 13-bit or 16-bit sample formats. FSC-BT806A supports: 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats. A sample rate of 8ksamples/s, 16ksamples/s or 32ksamples/s. Little or big endian bit order.
FSC-BT806 Datasheet Figure 25: PCM Master Timing Long Frame Sync Figure 26: PCM Master Timing Short Frame Sync Shenzhen Feasycom Technology Co., Ltd -33- www.feasycom.
FSC-BT806 Datasheet Figure 27: PCM Slave Timing Long Frame Sync Figure 28: PCM Slave Timing Short Frame Sync 4.8.5 I2S Controller The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. This Table lists these alternative functions. Shenzhen Feasycom Technology Co., Ltd -34- www.feasycom.
FSC-BT806 Datasheet Table 10: Alternative functions of the digital audio bus interface on the PCM interface PCM Interface I2S Interface PCM_OUT I2S_OUT PCM_IN I2S_IN PCM_SYNC I2S_WS PCM_CLK I2S_CLK Figure 29：Digital Audio Interface Modes Shenzhen Feasycom Technology Co., Ltd -35- www.feasycom.
FSC-BT806 Datasheet Figure 30：Digital Audio Interface Slave Timing Figure 31：Digital Audio Interface Master Timing 4.9 Programming and Debug Interface Important Note: The SPI is for programming, configuring (PS Keys) and debugging the FSC-BT806A. It is required in production. Ensure the 4 SPI signals are brought out to either test points or a header. Feasycom provides development and production tools to communicate over the SPI from a PC, although a level translator circuit is often required.
FSC-BT806 Datasheet 5. ELECTRICAL CHARACTERISTICS 5.1 Absolute Maximum Ratings Absolute maximum ratings for supply voltage and voltages on digital and analogue pins of the module are listed below. Exceeding these values causes permanent damage. The average PIO pin output current is defined as the average current value flowing through any one of the corresponding pins for a 100mS period.
FSC-BT806 Datasheet 5.3 Input/output Terminal Characteristics 5.3.1 Digital Table 13: DC Characteristics (VDD - VSS = 3 ~ 3.6 V, TA = 25C) Parameter Min Type Max Unit Input Voltage VIL - Standard IO Low level input voltage -0.4 - 0.4 V VIH - Standard IO Low level input voltage 0.7XVDD_IO - VDD_IO+0.4 V - - 25 nS - - 0.4 V 0.7XVDD_IO - - V - - 5 nS -150 -40 -10 uA Strong pull-down 10 40 150 uA Weak pull-up -5 -1.0 -0.33 uA Weak pull-down 0.33 1.0 5.
FSC-BT806 Datasheet Reduced headroom charge current,as a percentage of Ifast Mid, headroom =0.15V Charge current step size Vfloat threshold, calibrated Charge termination current Iterm, as percentage of Ifast 50 - 100 % - 10 - mA 4.16 4.20 4.24 V 7 10 20 % 100 - 150 mV - 50 - mV Min Type Max Unit 3.10 3.30 3.60 V Standby Mode Voltage hysteresis on VBAT_IN, Vhyst Error Charge Mode Headroom(a) error falling threshold (a) Headroom = VCC_CHG – VBAT_IN 5.3.
FSC-BT806 Datasheet 5.4 Stereo Codec 5.4.1 Analogue to Digital Converter Table 17: Analogue to Digital Converter Parameter Ccnditions Min Type Max Unit Resolution - - - 16 Bits Input Sample Rate, F sample - 8 - 48 KHz SNR f in = 1kHz B/W = 20Hz->F sample /2 (20kHz max) A-Weighted THD+N < 0.1% 1.6V pk-pk input 8kHz - 93 - dB 16kHz - 92 - dB 32kHz - 92 - dB 44.1kHz - 92 - dB 48kHz - 92 - dB 8kHz - 0.004 - % 48kHz - 0.
FSC-BT806 Datasheet 48kHz 32Ω - 0.003 - % 48kHz 16Ω - 0.004 - % Digital gain Digital gain resolution = 1/32 -24 - 21.5 dB Analogue gain Analogue Gain Resolution = 3dB -21 - 0 dB Output voltage Full-scale swing (differential) - - 778 mV rms - -88 - dB Stereo separation (crosstalk) 5.5 Auxiliary ADC Table 19: Auxiliary ADC Parameter Min Type Max Unit Resolution - - 10 Bits Input voltage range (a) 0 - 1.8 V -1 - 1 LSB 0 - 1 LSB -1 - 1 LSB -0.
FSC-BT806 Datasheet I2C Dynamic Characteristics 5.7 Table 21: I2C Dynamic Characteristics Parameter tLOW - SCL low period THIGH - SCL high period Standard Mode[1][2] Min Max Fast Mode[1][2] Min Max Unit 4.7 - 1.2 - uS 4 - 0.6 - uS 4.7 - 1.2 - uS tSU; STA time Repeated START condition setup tHD; STA - START condition hold time 4 - 0.6 - uS tSU; STO - STOP condition setup time 4 - 0.6 - uS 4.7[3] - 1.
FSC-BT806 Datasheet 5.8 PCM Dynamic Characteristics Table 22: PCM Dynamic Characteristics Parameter Min Typ Max Unit - 128 256 512 - KHz 2.
FSC-BT806 Datasheet I2S Dynamic Characteristics 5.9 Table 23: I2S Dynamic Characteristics Parameter Min Typ Max Unit SCK Frequency - - 6.2 MHz WS Frequency - - 9.6 KHz Digital Audio Interface Slave Timing tch - SCK high time 80 - - nS tcl - SCK low time 80 - - nS 20 - - nS 2.
FSC-BT806 Datasheet Bluetooth 2.1 Operation Mode Current Consumption, Power supply 3.3V Idle Power on, discoverable and connectable. ~3.6 mA Searching Searching devices ~6.3 mA Connected Standby Connected, no data traffic ~3.4 mA (e)SCO traffic Handsfree calling ~15 mA RX/TX active UART data traffic ~7 mA Bluetooth 4.0/5.0 Operation Mode Advertising Current Consumption, Power supply 3.3V Advertising ~3.8 mA Connected Standby Connected, no data traffic ~4.
FSC-BT806 Datasheet 7. RECOMMENDED TEMPERATURE REFLOW PROFILE Prior to any reflow, it is important to ensure the modules were packaged to prevent moisture absorption. New packages contain desiccate (to absorb moisture) and a humidity indicator card to display the level maintained during storage and shipment. If directed to bake units on the card, please check the below Table 27 and follow instructions specified by IPC/JEDEC J-STD-033. Note: The shipping tray cannot be heated above 65°C.
FSC-BT806 Datasheet each activator and rosin get activated and start eliminating oxide film formed on the surface of each solder particle and PCB board. The temperature is recommended to be 150 to 210 for 60 to 120 second for this zone. Equilibrium Zone 2 (C) (optional) — In order to resolve the upright component issue, it is recommended to keep the temperature in 210 – 217 for about 20 to 30 second. Reflow Zone (D) — The profile in the figure is designed for Sn/Ag3.0/Cu0.5.
FSC-BT806 Datasheet 9. HARDWARE INTEGRATION SUGGESTIONS 9.1 Soldering Recommendations FSC-BT806A is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations.
FSC-BT806 Datasheet 9.3 Layout Guidelines(External Antenna) Placement and PCB layout are critical to optimize the performances of a module without on-board antenna designs. The trace from the antenna port of the module to an external antenna should be 50 and must be as short as possible to avoid any interference into the transceiver of the module. The location of the external antenna and RF-IN port of the module should be kept away from any noise sources and digital traces.
FSC-BT806 Datasheet To reduce signal reflections, sharp angles in the routing of the micro strip line should be avoided. Chamfers or fillets are preferred for rectangular routing; 45-degree routing is preferred over Manhattan style 90-degree routing. Antenna Wrong Antenna Antenna PCB PCB PCB Better Best Figure 38: Recommended Trace Connects Antenna and the Module Routing of the RF-connection underneath the module should be avoided.
FSC-BT806 Datasheet Figure 39: Tray vacuum 10.2 Packing box(Optional) * If require any other packing, must be confirmed with customer * Package: 2000PCS Per Carton (Min Carton Package) Figure 40: Packing Box Shenzhen Feasycom Technology Co., Ltd -51- www.feasycom.
FSC-BT806 Datasheet 11. 11.1 APPLICATION SCHEMATIC Application circuit diagram(Default) Shenzhen Feasycom Technology Co., Ltd -52- www.feasycom.
FSC-BT806 Datasheet 11.2 Application circuit diagram(Earphone) FCC Warning Integration instructions for host product manufacturers according to KDB 996369 D03 OEM Manual v01 2.2 List of applicable FCC rules FCC Part 15.247 2.3 Specific operational use conditions This transmitter/module and its antenna(s) must not be co-located or operating in conjunction with any transmitter. This information also extends to the host manufacturer’s instruction manual. 2.4 Limited module procedures Not applicable 2.
FSC-BT806 Datasheet FCC/IC Statements (OEM) Integrator has to assure compliance of the entire end-product incl. the integrated RF Module. For 15 B (§15.107 and if applicable §15.109) compliance, the host manufacturer is required to show compliance with 15 while the module is installed and operating. Furthermore the module should be transmitting and the evaluation should confirm that the module's intentional emissions (15C) are compliant (fundamental / out-of-band).
FSC-BT806 Datasheet This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canada’s licence-exempt RSS(s). Operation is subject to the following two conditions: (1) This device may not cause interference. (2) This device must accept any interference, including interference that may cause undesired operation of the device.
