Data Sheet

FSC-BT806 Datasheet
Shenzhen Feasycom Technology Co., Ltd www.feasycom.com
-15-
The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset
will be performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET be applied for a
period greater than 5ms.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state. The PIOs have weak
pull-ups.
4.2.1 Digital Pin States on Reset
This table shows the pin states of FSC-BT806A on reset. PU and PD default to weak values unless specified otherwise.
Table 4: Pin States on Reset
Pin Name/Group
I/O Type
Full Chip Reset
USB_DP
Digital bidirectional
N/A
USB_DN
Digital bidirectional
N/A
BT_TX
Digital bidirectional with PU
Weak PU
BT_RX
Digital bidirectional with PU
Strong PU
BT_CTS
Digital bidirectional with PD
Weak PD
BT_RTS
Digital bidirectional with PU
Strong PU
SPI_CSB
Digital input with PU
Strong PU
SPI_CLK
Digital input with PD
Weak PD
SPI_MISO
Digital tristate output with PD
Weak PD
SPI_MOSI
Digital input with PD
Weak PD
RESET
Digital input with PU
Strong PU
I2S_IN
Digital bidirectional with PD
Weak PD
I2S_OUT
Digital bidirectional with PD
Weak PD
I2S_WS
Digital bidirectional with PD
Weak PD
I2S_CLK
Digital bidirectional with PD
Weak PD
RESET
Digital input with PU
Strong PU
PIO0,1,2,3,4,5,6,7,14,15
Digital bidirectional with PD
Weak PD
4.2.2 Status After Reset
The status of FSC-BT806A after a reset is:
Warm reset: baud rate and RAM data remain available
Cold reset: baud rate and RAM data not available
4.2.3 Automatic Reset Protection
FSC-BT806A includes an automatic reset protection circuit which restarts/resets CSR8670 WLCSP when an
unexpected reset occurs, e.g. ESD strike or lowering of RST#. The automatic reset protection circuit enables resets from
the VM without the requirement for external circuitry.