Data Sheet

FSC-BT806 Datasheet
Shenzhen Feasycom Technology Co., Ltd www.feasycom.com
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Slots and Sample Formats
FSC-BT806A receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations are
either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats.
16 clocks cycles for 8-bit, 13-bit or 16-bit sample formats.
FSC-BT806A supports:
13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
A sample rate of 8ksamples/s, 16ksamples/s or 32ksamples/s.
Little or big endian bit order.
For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a
programmable 3-bit audio attenuation compatible with some codecs.
Figure 24: 16-bit Slot Length and Sample Formats
Additional Features
FSC-BT806A has a mute facility that forces PCM_OUT to be 0. In master mode, FSC-BT806A is compatible with
some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running.