Data Sheet

FSC-BT825
深圳市飞易通科技有限公司 www.feasycom.com
After main 3.3V ramp up and 1.2V ramp up, the power management unit is enabled by the
power ready detection circuit. The power management unit enable s the Bluetooth block. The
Bluetooth firmware then initializes all circuits, included the UART. In addition to waiting the
Tnon_rdy time, if the host supports UART hardware flow control it can detect RTS signals
and follow the formal UART flow control handshake.
Min Tyupical Max Unit
T33ramp - - No Limit ms
Toff 250 500 1000
ms
T33ramp 0.1 0.5 2.5
ms
T12ramp 0.1 0.5 1.5
ms
TPOR 2 2 8
ms
Tnon_rdy 1 2 10
ms
Table 7: UART Interface Power On Timing Parameters
5.2 PCM CODEC Interface
The FSC-BT825 supports a PCM digital audio interface that is used for transmitting digital
audio/voice data to/from the Audio Codec. Features are supported as below:
● Supports Master and Slave mode
● Programmable long/short Frame Sy
nc
●
Supports 8-bit A-law/u-law, and 13/16-bit linear PCM form
ats
●
Supports Master and Slave mode
● Supports sign-extension and zero-padding for 8-bit and 13-bit sample
s
●
Supports padding of Audio Gain to 13-bit sample
s
●
PCM Master Clock Output: 64, 128, 256, or 51
2kHz
●
Supports Master and Slave mode
●
Suppo
rts SCO/ESCO li
nk
Shenzhen Feasycom Technology
C
o.,Ltd