Data Sheet

FSC-BT836B
Shenzhen Feasycom Technology Co.,LTD www.feasycom.com
Figure 3: SPI timing diagram - slave mode and CPHA = 0
* 1. Measurement points are done at CMOS levels: 0.3 VDDand 0.7 VDD.
Figure 4: SPI timing diagram - slave mode and CPHA = 1