Data Sheet

FSC-BT956B Datasheet
Shenzhen Feasycom Technology Co., Ltd www.feasycom.com
-14-
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each
data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An
acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA
line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A
transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the following
figure for more details about I2C Bus Timing.
Figure 6: I2C Bus Timing
The device on-chip I2C logic provides the serial interface that meets the I2C bus standard mode specification. The I2C
port handles byte transfers autonomously. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL. Pull up
resistor is needed for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must set
the pins function to I2C in advance.
4.6.3 USB Device Controller
FSC-BT956B has a full-speed USB interface for communicating with other devices, such as PC or USB card. Bothe USB
PHY and Link layer is integrated. It supports both host and device. USB role detection is included to support USB Type
A.
Operates either as the host/peripheral in point-to-point communications with another USB function or as a
function controller for a USB peripheral
Complies with the USB 1.1 standard for high-speed (12 Mbps) functions
Supports point-to-point communications with one high-, full- or low-speed device
Supports Control, Interrupt, Bulk and Isochronous transfer
4 Endpoint with FIFOs
One Bi-directional Control Endpoint (EP0)
Four soft configurable Bi-directional Endpoints