Data Sheet

FSC-BT956B Datasheet
Shenzhen Feasycom Technology Co., Ltd www.feasycom.com
-20-
5.6 I2C Dynamic Characteristics
Table 10: I2C Dynamic Characteristics
Parameter
Standard Mode[1][2]
Fast Mode[1][2]
Unit
Min
Max
Min
Max
t
LOW
- SCL low period
4.7
-
1.2
-
uS
T
HIGH
- SCL high period
4
-
0.6
-
uS
t
SU; STA
- Repeated START condition setup
time
4.7
-
1.2
-
uS
t
HD; STA
- START condition hold time
4
-
0.6
-
uS
t
SU; STO
- STOP condition setup time
4
-
0.6
-
uS
t
BUF
- Bus free time
4.7[3]
-
1.2[3]
-
uS
t
SU;DAT
- Data setup time
250
-
100
-
uS
t
HD;DAT
- Data hold time
0[4]
3.45[5]
0[4]
0.8[5]
uS
t
r
- SCL/SDA rise time
-
1000
20+0.1CB
300
uS
t
f
- SCL/SDA fall time
-
300
-
300
uS
C
b
- Capacitive load for each bus line
-
400
-
400
pF
Note:
1. Guaranteed by design, not tested in production.
2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be higher than 8
MHz to achieve the maximum fast mode I2C frequency.
3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined
region of the falling edge of SCL.
5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of
SCL signal.
Figure 9: I2C Timing Diagram