Hardware Guide
Table Of Contents
- Fibocom_FM101-CG_Hardware_Guide_V1.0.pdf
- FM101-CG-20: Hardware Guide
- Contents
- Change History
- 1. Foreword
- 2. Product Overview
- 3. Pin Definition
- 4. Electrical Characteristics
- 5. Functional Interface
- 6. Radio Frequency
- 6.1. RF Interface
- 6.2. Operating Bands
- 6.3. Transmitting Power
- 6.4. Receiving Sensitivity
- 6.5. GNSS Receiving Performance
- 6.6. Antenna Design
- 6.7. PCB Routing Design
- 6.8. Main Antenna Design
- 6.9. Diversity and MIMO Antenna Design
- 6.10. GNSS Antenna Design
- 6.11. Other Interfaces
- 7. Thermal Design
- 8. Electrostatic Protection
- 9. Structural Specifications
- Appendix A: Acronyms and Abbreviations
- Module FCC & ISED警语 for Fibocom
Figure 14. Reference circuit of the PCM interface external Codec chip
5.8. PCIe Interface
FM101-CG module supports a group of PCIe GEN 2.0 x 1 lanes.
Table 23. PCIe pin definition
Pin Name I/O
Pin
Number
Description
PETn0 DO 41
PCIe data transmitting signal negative
PETp0 DO 43 PCIe data transmitting signal positive
PERn0 DI 47 PCIe Data receiving signal negative
PERp0 DI 49 PCIe Data receiving signal positive
PERST# DI 50 PCIe mode reset signal
CLKREQ# DIO 52
PCIe clock request signal with
external pull-up
REFCLKN DIO 53 PCIe reference clock signal negative
PEWAKE# DO 54
PCIe RC mode wake-up signal with
external pull-up
REFCLKP DIO 55 PCIe reference clock signal positive
5. Functional Interface
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