Hardware Guide

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FIBOCOM L860-GL-16

Hardware Guide

Version: 1.0.0

Date: 2020-09-28

Fibocom

Confidential

Summary of content (60 pages)

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Fi nf bo id co en m ti al FIBOCOM L860-GL-16 Hardware Guide Version: 1.0.
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Copyright Copyright © 2019 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or distribute the document in any form. Notice The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide.
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End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: “Contains FCC ID: ZMOL860GL16” “Contains IC: 21374-L860GL16 “ The FCC ID/IC ID can be used only when all FCC/IC compliance requirements are met.
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The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules.
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module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed.
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Change History Author Date Remark V1.0.0 Shu Ying 2020-09-28 Draft version Co Fi nf bo id co en m ti al Version Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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Contents 2 3 Foreword ......................................................................................................................10 1.1 Introduction................................................................................................................. 10 1.2 Reference Standard ................................................................................................... 10 1.3 Related Documents ................................................................................
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3.5.2.2 N.O. SIM Card Slot .................................................................................................................... 39 USIM Hot-Plug .............................................................................................................. 39 USIM Design ................................................................................................................. 40 3.6 Status Indicator....................................................................................
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1 Foreword 1.1 Introduction The document describes the electrical characteristics, RF performance, dimensions and application environment, etc. of L860-GL-GL (hereinafter referred to as L860). With the assistance of the document and other instructions, the developers can quickly understand the hardware functions of L860 modules and develop products. 1.2 Reference Standard  Fi nf bo id co en m ti al The design of the product complies with the following standards: 3GPP TS 34.121-1 V8.11.
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2 Overview 2.1 Introduction L860 is a highly integrated 4G WWAN module which uses M.2 form factor interface. It supports LTE FDD/LTE TDD/WCDMA systems and can be applied to most cellular networks of mobile carrier in the world. 2.
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Specification Support 4×4 MIMO Dual SIM, 1.8V/3V PCIe 2.0×1 USB 2.0 (For debug) USB 3.0 (For debug) Function Interface W_Disable# BodySAR LED Fi nf bo id co en m ti al Tunable antenna UART Software Protocol Stack IPV4/IPV6 AT Commands 3GPP TS 27.007 and 27.005 Firmware Update PCIe Multiple carrier Other Feature Windows MBIM support Windows update OS Windows10/Linux/Android Note:  B42 disabled as of FCC certification, support pending regulatory approval.
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2.
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DL CA Combination 4+46+46+46, 5+5+30+66, 5+46+46+66, 13+46+46+66, 66+46+46+46, 13+48+66+66,13+48+48+66, 2 intra-band (contiguous) plus 2 intra-band (contiguous) 2 intra-band (contiguous) plus 2 intra-band (non-contiguous) 3 intra-band (contiguous) plus inter-band 5+5+66+66,5+5+46+46,7+7+46+46,48+48+66+66, 5+5+66+66,2+2+46+46,46+46+66+66, 2+2+5+5,2+2+66+66,4+4+5+5,48+48+66+66, 2+46+46+46, 3+40+40+40, 4+46+46+46, 5+46+46+46, 13+46+46+46, 25+41+41+41, 66+46+46+46,7+46+46+46, 41 Intra-band (contiguous) 2 intr
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2.4 Application Framework The peripheral applications for L860 module are shown in Figure 2-1: D/G(AUX1) ANT M2(AUX3) ANT M1(AUX2) ANT Main ANT Fi nf bo id co en m ti al Module Power Supply ON/OFF# RESET# SIM1 e-SIM PCIe SIM Card Control USB2.0 EINT Indicator Host application Figure 2-1 Application framework 2.5 Hardware Block Diagram The hardware block diagram in Figure 2-2 shows the main hardware functions of L860 module, including baseband and RF functions.
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+3.3V M.2 Key-B 75pin interface TCXO PMU RF Part NAND Main RX Duplexer UB PA SAW Main HB FEMiD LPDDR4 RAM RESET# XB LNA TRX SAW Tiplexer FULL_CARD_POWER_OFF# M (Main) ANT RF SAW PCIe Main MB FEMiD TX USB2.0 USB3.
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3 Application Interface 3.1 M.2 Interface The L860 module applies standard M.2 Key-B interface, with a total of 75 pins. Pin Map 74 +3.3V 72 +3.3V 70 68 75 VIO_CFG 73 GND 71 CONFIG_1 69 RESET#(1.8V) 67 ANTCTL3(1.8V) 65 +3.3V ANT_CONFIG(1.8V) SIM1_DETECT(1.8V) Fi nf bo id co en m ti al 66 CONFIG_2 64 COEX_TXD(1.8V) 62 COEX_RXD(1.8V) 60 58 56 CLKREQ# (3.3V) NC 44 I2C_IRQ#(1.8V) REFCLKN 53 GND 51 PERp0 49 PERn0 47 GND 45 PETp0 43 PETn0 41 GND 39 USB3.
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Pin Definition The pin definition is as follows: Pin Pin Name I/O Reset Value Pin Description Type NC, L860 M.2 module is configured as 1 CONFIG_3 O NC the WWAN – PCIe, USB3.0 interface type +3.3V PI - Power input Power Supply 3 GND - - GND Power Supply 4 +3.
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Pin Pin Name I/O Reset Value 23 WOWWAN# O PD 24 ANT_TUNER_1V8 PO IO Pin Description Wake up host, Reserved 1.8V output for ANT Tuner PD GPIO(High-z) UART_CTS (Reserved) 1.8V Power Supply /1.8V 25 DPR I PD 26 W_DISABLE2# I PD 27 GND - - GND Power Supply 28 UART_RX I PD UART_RX, MUX for GPIO(High-z) 1.8V USB3.0_TX- O UIM_RESET O USB3.0_TX+ O UIM_CLK O L SIM clock signal 1.8V/3V GND - - GND Power Supply UIM_DATA I/O L SIM data input/output 1.8V/3V USB3.
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Pin Pin Name 46 NC 47 PERn0 48 NC 49 PERP0 I/O Reset Value Pin Description Type NC PCIe RX differential signal I Negative NC PCIe RX differential signal I Positive Asserted to reset module PCIe interface default. If module went into 50 PERST# I PU core dump, it will reset whole module, 3.3V Fi nf bo id co en m ti al not only PCIe interface.
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Pin Pin Name I/O Reset Value Pin Description Type 59 ANTCTL0 O L Tunable ANT CTRL0 1.8V Wireless coexistence between WWAN 60 COEX3 I/O PD and WIFI/BT modules, based on BT-SIG coexistence protocol. COEX_EXT_FTA, 1.8V Reserved 61 ANTCTL1 O PD Tunable ANT CTRL1 1.8V Wireless coexistence between WWAN 62 COEX_RXD I T and WIFI/BT modules, based on BT-SIG coexistence protocol. UART receive 1.
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Pin Pin Name I/O Reset Value Pin Description Type NC, L860 M.2 module is configured as 75 CONFIG_2 O NC the WWAN – PCIe, USB3.0 interface - type Reset Value: The initial status after module reset, not the status when working. H: High Voltage Level  L: Low Voltage Level  PD: Pull-Down  PU: Pull-Up  T: Tristate  OD: Open Drain   Fi nf bo id co en m ti al  PI: Power Input PO: Power Output Note: The unused pins can be left floating. 3.
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Power Supply The L860 module should be powered through the +3.3V pins, and the power supply design is shown in Fi nf bo id co en m ti al Figure 3-2: Figure 3-2 Power supply design The filter capacitor design for power supply is shown in the following table: Recommended Capacitance Application Description Reduce power fluctuations of the module in operation, requiring capacitors with low ESR.
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The stable power supply can ensure the normal operation of L860 module. The ripple of the power supply should be less than 300mV in design. Because module support 5CA download. When module operates with the maximum data transfer throughput, the peak current can reach to upper 2500mA. It requests the power source voltage should not be lower than 3.135V, otherwise module may shut down or restart.
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Power Consumption In the condition of 3.3V power supply, the L860 power consumption is shown in the following table: Typical Parameter Mode Condition Ioff Power off Power supply, module power off 0.02 DRX=6 5.5 DRX=8 3.5 DRX=9 3.3 Paging cycle #128 frames (1.28s DRx cycle) 5.3 WCDMA ISleep Fi nf bo id co en m ti al LTE FDD Current (mA) IWCDMA-RMS LTE TDD Paging cycle #128 frames (1.28s DRx cycle) 5.3 Radio Off AT+CFUN=4, flight mode 2.8 WCDMA Data call Band 2 @+23.
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Typical Parameter Mode Condition Current (mA) LTE TDD Data call Band 41 @+23dBm 620 LTE TDD Data call Band 48 @+21dBm 400 Note： The above data is the average value obtained by testing the sample for high/medium/low channels.
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Pin Pin Name I/O Reset Value Function Type Asserted to reset module PCIe interface default. If module went into 50 PERST# I PU 3.3V core dump, it will reset whole module, not only PCIe interface. Active low, internal pull up (10KΩ) Note： RESET# and PERST# need to be controlled by independent GPIO, and not shared with other devices on the host. RESET# and PERST# are sensitive signals, so they should keep away from RF interference and be protected by GND.
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tpr +3.3V FCPO# ton1 RESET# ton2 PERST# typical 15s Module State OFF Initialization Activation(AT Command Ready) Figure 3-5 Timing control for start-up Min. Recommended Max. tpr 0ms - - ton1 8ms 20ms - ton2 50ms 100ms - Comment Fi nf bo id co en m ti al Index The delay time of power supply rising from 0V up to 3.135V.
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tpd +3.3V FCPO# toff2 RESET# toff1 AT+CFUN=0 PERST# tsd Module State Activation Finalization OFF Fi nf bo id co en m ti al Figure 3-6 Shutdown timing control Index Min. Recommended Max. Comment toff1 16ms 20ms - RESET# should be asserted after PERST# toff2 2ms 10ms - FCPO# should be asserted after RESET# tpd 10ms 100ms - +3.3V power supply goes down time.
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Fi nf bo id co en m ti al Figure 3-7 Recommended design for reset circuit There are two reset control timings as below:  Reset timing 1st in Figure 3-8, PMU of module internal always on in reset sequence, recommend using in FW upgrade and module recovery;  Reset timing 2nd in Figure 3-9, PMU of module internal will be off in reset sequence (including whole power off and power on sequence, tsd can refer section 3.3.2), recommend using in system warm boot. +3.
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+3.3V toff FCPO# toff2 RESET# ton1 toff1 AT+CFUN=0 ton2 PERST# typical 15s tsd Module State Activation Finalization OFF Initialization Activation Figure 3-9 Reset control timing2nd Min. Recommended Max. toff1 16ms 20ms - toff2 2ms 10ms - Comment Fi nf bo id co en m ti al Index RESET# should be asserted after PERST#, refer section 3.3.2 FCPO# should be asserted after RESET#, refer section 3.3.
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PCIe Link State 3.3.4.1 PERST# CLKREQ# L L Power Consumption (mA) Isleep+0.8 Description The extra 0.3mA is consumed on CLKREQ# pull down D0 L1.2 Module supports PCIe goes into D0 L1.2 state in Win10 system. The D0->D0 L1.2@S0/S0ix->D0 timing is shown in Figure 3-10: +3.3V Fi nf bo id co en m ti al FCPO# RESET# PERST# CLKREQ# Module State D0 L0@S0/S0ix D0 L1.2@S0/S0ix D0 L0@S0/S0ix Figure 3-10 D0 L1.2 timing 3.3.4.
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+3.3V FCPO# RESET# PERST# Host assert Host de-assert CLKREQ# Fi nf bo id co en m ti al PEWAKE# Module State D0 L0@S0/S0ix D3cold L2@S0/S0ix D0 L0@S0/S0ix Figure 3-11 D3cold L2 timing (Host wakeup) +3.3V FCPO# RESET# PERST# Host assert Host de-assert CLKREQ# PEWAKE# Module State Modem assert D0 L0@S0/S0ix D3cold L2@S0/S0ix Modem de-assert D0 L0@S0/S0ix Co Figure 3-12 D3cold L2 timing (Modem wakeup) Reproduction forbidden without Fibocom Wireless Inc.
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Timing Application The recommended timing application in Win10 OS is as below table: System status Timing Application D0 L1.2 S0ix (Modem standby) D3cold L2 Power on Refer to section 3.3.4.1 Figure 3-10 D0 L1.2 timing Refer to section 3.3.4.2 Figure 3-11/3-12 D3cold L2 timing Refer to section 3.3.1.2 Figure 3-5 Timing control for start-up (back to S0) S3, S4, S5 Power off (out of S0) Power on Refer to section 3.3.1.
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PCIe Interface Definition Pin# Pin Name I/O Reset Value Description 41 PETn0 O - PCIe TX differential signal Type - Negative 43 PETP0 O - PCIe TX differential signal - Positive 47 PERn0 I - PCIe RX differential signal - Negative PERP0 I - PCIe RX differential signal - Fi nf bo id co en m ti al 49 Positive 53 REFCLKN I - PCIe reference clock signal - Negative 55 REFCLKP I - PCIe reference clock signal - Positive Asserted to reset module PCIe interface 50 PERST#
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PCIe Interface Application The reference circuit is shown in Figure 3-12: AP side Module side AC Caps PERn0 PETn0 AC Caps PETP0 REFCLKN REFCLKP PETP0(pin43) PERn0(pin47) PERP0(pin49) REFCLKN(pin53) REFCLKP(pin55) Fi nf bo id co en m ti al +3.3V/1.8V M.
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serpentine line and another one of the differential lines must be less than 2 times the spacing of normal differential lines (S1 < 2S). ≥1.5W ≥3W W PCIe Difference Pair 1 ≥ S 5° 13 S1<2S ≥20mil Fi nf bo id co en m ti al PCIe Difference Pair 2 Figure 3-13 Requirement of PCIe line The difference in length of two data lines in difference pair should be within 5mil, and the length match is required for all parts.
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USIM1 Pins The USIM1 pins description is shown in the following table: Pin Pin Name I/O Reset Value Description Type 36 UIM_PWR PO - USIM power supply 1.8V/3V 30 UIM_RESET O L USIM reset 1.8V/3V 32 UIM_CLK O L USIM clock 1.8V/3V 34 UIM_DATA I/O L USIM data, internal pull up (4.7KΩ) 1.8V/3V USIM card detect, internal 390K pull-up. SIM_DETECT I PD Active high, and high level indicates SIM card is inserted; and low level indicates 1.
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3.5.2.2 N.O. SIM Card Slot Fi nf bo id co en m ti al The reference circuit design for N.O. (Normally Open) SIM card slot is shown in Figure 3-16: Figure 3-16 Reference circuit for N.O. SIM card slot The principles of the N.O.SIM card slot are described as follows:  When the SIM card is detached, it connects an open circuit between CD and SW pins, and drives the SIM_DETECT pin low.
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when the SIM_DETECT pin is high, then executes the initialization program and finish the network registration after reading the SIM card information. When the SIM_DETECT pin is low, the module determines that the SIM card is detached and does not read the SIM card. Note: SIM_DETECT is active high. It can be swapped to active low by AT CMD.
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The LED driving circuit is shown in Figure 3-17: Fi nf bo id co en m ti al Figure 3-17 LED driving circuit Note: The resistance of LED current-limiting resistor is selected according to the driving voltage and the driving current. WOWWAN# The WOWWAN# signal is used to wake the Host (AP) when there comes the data request. The definition of WOWWAN# signal is as follows: Operating Mode WOWWAN# Signal SMS or data requests Pull low 1s then pull high (pulse signal).
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3.7 Interrupt Control The L860 module provides four interrupt signals, and the pin definition is as follows: Pin Pin Name I/O 8 W_DISABLE1# I 25 DPR 26 68 Reset Pin Description Type PD Enable/Disable RF network 3.3/1.8V I PD BodySAR detection 3.3/1.8V W_DISABLE2# I PD ANT_CONFIG I PD Value GNSS disable signal Reserved 3.3/1.8V Host antenna configuration 1.
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ANT_CONFIG L860 module can be configured to support dual antennas or 4 antennas by detecting the ANT_CONFIG pin. ANT_CONFIG is an input port which is pulled high internal in default. When ANT_CONFIG is high level, then module supports dual antennas (Main & D/G ANT). When module detects low level of ANT_CONFIG, then module will be configured to support 4 antennas.
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3.9 Configuration Interface The L860 module provides four pins for the configuration as the WWAN-PCIe, type M.2 module: Pin Pin Name I/O Reset Value Pin Description Type 1 CONFIG_3 O - NC - 21 CONFIG_0 O - NC - 69 CONFIG_1 O L Internally connected to GND - 75 CONFIG_2 O - NC - Fi nf bo id co en m ti al The M.
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4 Radio Frequency 4.1 RF Interface RF Interface Functionality The L860 module supports four RF connectors used for external antenna connection. As the Figure 4-1 shows, “M” is for Main antenna, which is used to receive and transmit RF signal; “D/G” is for Diversity antenna, which is used to receive the diversity RF signal. “M1” and “M2” are used for support 4x4 MIMO Fi nf bo id co en m ti al data transfer.
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Fi nf bo id co en m ti al following picture: Figure 4-2 RF connector dimensions Co Figure 4-3 0.81mm coaxial antenna dimensions Figure 4-4 Schematic diagram of 0.81mm coaxial antenna connected to the RF connector Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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RF Connector Assembly Fi nf bo id co en m ti al Mate RF connector parallel refer Figure 4-5, do not slant mate with strong force. Figure 4-5 Mate RF connector To avoid damage in RF connector unmating, it is recommended using pulling JIG as Figure 4-6, and the pulling JIG must be lifted up vertically to PCB surface (see Figure 4-7 and 4-8). Co Figure 4-6 Pulling JIG Figure 4-7 Lift up pulling JIG Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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Fi nf bo id co en m ti al Figure 4-8 Pulling direction 4.
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Description Mode Tx (MHz) Rx (MHz) Band 66 1700MHz LTE FDD 1710-1780 2110-2200 Band 71 680MHz LTE FDD 663-698 617-652 Band 38 2600MHz LTE TDD 2570-2620 Band 41 2500MHZ LTE TDD 2496-2690 Band 48 3600MHZ LTE TDD 3550-3700 Band 46 5200MHZ LTE TDD N/A 5150-5925 GPS L1 - - - 1575.42±1.023 GLONASS L1 - - - 1602.5625±4 Fi nf bo id co en m ti al Operating Band BDS - - - 1561.098±2.046 Galileo - - - 1575.42±1.023 4.
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Mode LTE TDD Band 3GPP Requirement (dBm) Tx Power (dBm) Note Band 66 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 71 23+2.7/-3.2 23+2/-1 10MHz Bandwidth, 1 RB Band 38 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 41 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 41 HPUE 26±2.7 25+2/-1 10MHz Bandwidth, 1 RB Band 48 23+3/-4 21±1 10MHz Bandwidth, 1 RB Fi nf bo id co en m ti al 4.
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Mode Band 3GPP Requirement (dBm) Rx Sensitivity (dBm) Typical Note Band 66 -95.8 -101.5 10MHz Bandwidth Band 71 -93.5 -101.4 10MHz Bandwidth Band 38 -96.3 -100.2 10MHz Bandwidth Band 41 -94.3 -99.4 10MHz Bandwidth Band 46 -88.5 -95.5 20MHz Bandwidth Band 48 -95 -101.3 10MHz Bandwidth LTE TDD Note: Fi nf bo id co en m ti al The above values are measured in dual antennas condition (Main+Diversity).
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4.5 GNSS L860 module supports GPS/GLONASS/BDS/Galileo and adopts RF Diversity and GNSS integrated antenna. Test Result Description Condition Max Typical GPS fixing 80mA @ -130dBm 65mA @ -130dBm GPS tracking 80mA@ -130dBm 65mA@ -130dBm GPS+GLONASS+ 80mA @ -130dBm 65mA @ -130dBm Fi nf bo id co en m ti al BDS fixing Current GPS+GLONASS+ 80mA @ -130dBm 65mA @ -130dBm GPS Sleep 3.5mA 2mA GPS+GLONASS+ 3.
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L860 Module Main Antenna Requirement Frequency range The most proper antenna to adapt the frequencies should be used.
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5 ESD Characteristics The module is generally not protected against Electrostatic Discharge (ESD). ESD handling precautions that apply to ESD sensitive components should be strictly followed. Proper ESD handling procedures must be applied throughout the processing, handling, assembly and operation of any application with module. The ESD characteristics are shown in the following table (Temperature: 25°C, Relative Humidity: 40%).
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6 Structure Specification 6.1 Product Appearance Fi nf bo id co en m ti al The product appearance for L860 module is shown in Figure6-1: Figure 6-1 Module appearance Note The label of each module is subject to the good shipped. 6.2 Dimension of Structure Co The structural dimension of the L860 module is shown in Figure 6-2: Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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Fi nf bo id co en m ti al Figure 6-2 Dimension of structure 6.3 M.2 Interface Model The L860 M.2 module adopts 75-pin gold finger as external interface, where 67 pins are signal pins and 8 pins are notch pins as shown in Figure 3-1. For module dimension, please refer to 6.2 Dimension of Structure. Based on the M.2 interface definition, L860 module adopts Type 3042-S3-B interface (30x42mm, Co the component maximum height on t top layer is 1.5mm, PCB thickness is 0.8mm, and KEY ID is B).
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Fi nf bo id co en m ti al Figure 6-3 M.2 interface model 6.4 M.2 Connector L860 module connects with host by M.2 connector which is built in host. The recommended part number is APCI0026-P001A manufactured by LOTES Corporation, and the dimension is shown in Figure 6-4. The Co package of connector, please refer to the specification. Figure 6-4 M.2 dimension of structure Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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6.5 Storage Storage Conditions (recommended): Temperature is 23±5°C, relative humidity is less than RH 60%. Storage period: Under the recommended storage conditions, the storage life is 12 months. 6.6 Packing The L860 module uses the tray sealed packing, combined with the outer packing method using the hard cartoon box, so that the storage, transportation and the usage of modules can be protected to the greatest Fi nf bo id co en m ti al extent.
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Tray Size Fi nf bo id co en m ti al The pallet size is 315×170×6.5mm, and is shown in Figure 6-6: Figure 6-6 Tray size (unit: mm) ITEM DIM (Unit: mm) L 315.0±2.0 H T A B C D E F G 170.0±2.0 6.5±0.3 0.8±0.1 43.0±0.3 31.0±0.3 79.0±0.2 Co W 60.0±0.2 180.0±0.2 60.0±0.2 40.0±0.2 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.