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FIBOCOM SC138-EAU Series Hardware Guide 1/88

FIBOCOM LTE Module (SC138-NA

Series)

Hardware Guide

Version: V1.0.1

Date: 2021-04-18

Summary of content (88 pages)

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Copyright Copyright ©2020 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or transmit the document in any form. Note The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide.
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Revision History Version Author Reviewer V1.0.0 Tan Qiuye Tu Min Ye Xincai V1.0.1 Huang Feng Approver Chen Guojiang Tu Min Chen Li Xiyi Guojiang Date Description 2020-12-29 Initial version First revision, Adding W-20 2021-04-18 version; Updating some RF parameters. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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Contents 1 2 3 About This Document ...................................................................................................8 1.1 Description ....................................................................................................................... 8 1.2 References ...................................................................................................................... 8 1.3 Related Documents ........................................................................
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3.13 Battery Power Supply Interface ...................................................................................... 52 3.14 Motor Drive Interface ..................................................................................................... 52 3.15 LCM ............................................................................................................................... 52 3.16 TP ..........................................................................................................
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6 7 8 9 5.3 Bluetooth Overview ........................................................................................................ 76 5.4 Bluetooth Performance Indicators .................................................................................. 77 GNSS ............................................................................................................................78 6.1 Overview ................................................................................................
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1 About This Document 1.1 Description The document describes information on electrical characteristics, RF performance, structural dimension, application environment, etc. of SC138-NA series modules. With the help of this document and other related documents, the application developer can quickly understand the hardware functions of SC138NA series modules and develop the hardware of the product. 1.2 References This product is designed with reference to the following standards:  3GPP TS 51.010-1 V10.5.
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2007  IEEE Std 802.11b, IEEE Std 802.11n, IEEE Std 802.11a, IEEE Std 802.11g, IEEE Std 802.11ac  IEEE 802.11-2007 WLAN MAC and PHY, June 2007  Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+ EDR/3.0/3.0+  HS, August 6, 2009  Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009  Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/5.0.2, December 07,2017 Reproduction forbidden without Fibocom Wireless Inc.
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2 Product Overview 2.1 Product Introduction SC138 series intelligent modules integrate core devices such as Baseband, eMCP, PMU, Transceiver and PA, and support remote communication modes of FDD/TDD-LTE, WCDMA, and multiple types, WIFI/BT short-range wireless transmission technology and GNSS wireless positioning technology(SC138-W support WiFi/BT only).
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Table 2-2 Performance and specification Performance Power supply Application processor Storage Description DC 3.5 V–4.2 V Typical voltage: 3.
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Performance Description 1 set of DP over type-C interface with developing functions Camera interface 3 sets of 4-Lane MIPI_CSI interfaces, with the maximum rate up to 2.5 Gbps per Lane, which supports the maximum 25 MP pixel. Audio input: 3 sets of analog MIC inputs Internal integration bias Audio interface Audio output: Class AB stereo earphone output Class AB differential handset output Class D differential speaker power amplifier output USB 2.
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Performance Description ADC interface Universal 15-bit precise ADC RTC Supported Antenna interface TRX antenna, DRX antenna, GNSS antenna and WIFI/BT antenna interfaces Dimensions: 41mm × 41mm × 2.8mm Physical characteristics Package: 148 LCC + 128 LGA Weight: 9.6±1g Operating temperature: –30°C to 75°C1) Temperature range ） Expansion temperature: –40°C~85°C 2 Storage temperature: –40°C to 85°C Software upgrade USB/OTA/SD RoHS Conform to RoHS standard.
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Subpart B, the host manufacturer is required to show compliance with Part 15 Subpart B while the transmitter module(s) are installed and operating. The modules should be transmitting and the evaluation should confirm that the module's intentional emissions are compliant (i.e. fundamental and out of band emissions).
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Technical WCDMA/LTE WCDMA/LTE LTE Bluetooth WiFi B2/4/7/25/41/66 B5/12/13/14/17/26/71 B48 Antenna 1dBi 0.5dBi -0.13dBi WiFi 2.4G 5G 1dBi 1dBi 2dBi Gain Antenna Dipole type In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC/IC authorization is no longer considered valid and the FCC ID/IC ID cannot be used on the final product.
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interference by one of the following measures: - Reorient or relocate the receiving antenna. - Increase the separation between the equipment and receiver. - Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. - Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment.
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Radiation Exposure Statement This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body. Déclaration d'exposition aux radiations Cet équipement est conforme Canada limites d'exposition aux radiations dans un environnement non contrôlé. Cet équipement doit être installé et utilisé à distance minimum entre le radiateur et votre de 20cm corps.
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2.3 Pin Definition 2.3.1 Pin Distribution Note: "NC" stands for No Connect. The pin at this position is reserved, and no connection is required. 2.3.2 Pin Description Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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Table 2-3 Description of I/O parameters Type Description IO Input/output DI Digital input DO Digital output PI Power input PO Power output AI Analog input AO Analog output OD Open drain The pins of SC138 modules are described in the following table: Pin Name Pin No. I/O Pin Description Remarks VBAT 4,5,6 PI Main power supply input - VRTC 126 PI/PO RTC power supply pin - 226 PO 1.1 V voltage output - 129 PO 1.8 V voltage output - 122 PO 1.
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Pin Name Pin No. I/O Pin Description P8 Remarks adaption VREG_CAM0_ AVDD_2P8 VREG_CAM1_ 2_AVDD_2P8 VREG_CAM1_ 2_DVDD_1P2 VREG_ALS_VL ED_3P0 VREG_3P0 130 PO 2.8 V voltage output - 222 PO 2.8 V voltage output - PO 1.2 V voltage output, camera 264 265 266 power supply PO 3.0 V voltage output, light sensor power supply PO - - 3.0 V voltage output - 3.
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Pin Name Pin No. I/O Pin Description Remarks which can be configured for low level shutdown and restart; do not pull up externally.
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Pin Name Pin No.
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Pin Name Pin No. I/O Pin Description 267 OD I2C data line USB_IN_DET 168 PI VBUS input Detection - USB_DP 12 I/O USB 2.0 differential data signal+ - USB_ DM 11 I/O USB 2.
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Pin Name Pin No.
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Pin Name GPIO_127/I2S1 _DATA0 GPIO_128/I2S1 _DATA1 GPIO_118/MCL K2 Pin No.
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Pin Name Pin No. I/O Pin Description Remarks LCD0_RST_N 49 DO Main TP reset signal - PWM 44 DO LCD backlight PWM control - LCD_BL_EN 211 DO LCD backlight enabling control - LCD_TE 50 DI LCD refreshing synchronization NC when it is signal not in use.
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Pin Name Pin No.
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Pin Name Pin No.
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Pin Name Pin No.
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Pin Name Pin No. I/O Pin Description Remarks ADC Interface It can be ADC 128 AI ADC detection configured as 0.3 V-VBAT. Forced Downloading Script The high level (1.8 V) is FORCE_USB_ BOOT effective, and 1 DI Forced downloading the module cannot be pulled up before starting.
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Pin Name Pin No.
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Pin Name Pin No. I/O Pin Description Remarks 2,8,9,14,37,124,125,127,151,159,166,167,169,192,193,194, NC 195,198,199,200,201,202,203,223,225,227,234,242,248,25 2 N Hanging in the C air Note: Pins marked with "Boot configuration" do not allow hardware pull-up. Use CPU GPIO first, not PM6125_GPIO until there is no CPU GPIO.
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210 GPIO_27 88 GPIO_28 87 GPIO_29 104 GPIO_30 86 GPIO_31 96 GPIO_32 97 GPIO_33 L5 - SPI_CS2 - - QUP1 L0 - I2C_SDA - - SE2 L1 - I2C_SCL - - L0 UART_CTS SPI_MISO I2C_SDA - QUP1 L1 UART_RFR SPI_MOSI I2C_SCL - SE1 L2 UART_TX SPI_SCLK - - L3 UART_RX SPI_CS_N - - Note: Only one protocol can be selected in one QUP engine at a time. For example, simultaneous UART and I2C functionality are no longer supported. Reproduction forbidden without Fibocom Wireless Inc.
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3 Application Interface 3.1 Power SC138 provides 3 VBAT pins for connecting external power supply to the module. The range of power input voltage is 3.5 V-4.2 V, and the recommended value is 3.8 V. The performance of module power supply, such as load capacity and ripple size, will directly affect the performance and stability of the module during normal operation. The peak current of the module can reach 3 A under limiting cases.
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Table 3-1 Power supply Parameters Minimum Value VBAT (DC) 3.5 Recommended Value 3.8 Maximum Value Unit 4.2 V Note: The supply voltage of VBAT must be in the range of 3.5 V-4.2 V. If the supply voltage is lower than 3.5V, the system may be unstable. If the supply voltage is higher than 4.2 V, the hardware may be damaged or even destroyed. The reference design of power supply circuit is shown in the following figure: VBAT M odule + 220uF 220uF 1uF 100nF 39pF 33pF 18pF 8.2pF 6.
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Recommended Capacitance Application Description 1uF, 100nF Filter capacitance 39pF, 33pF, 18pF, 8.2pF, Decoupling 6.8pF capacitance Filter out the interference caused by clock and digital signal. Filter out high-frequency interference. 3.1.2 VRTC VRTC supplies power for the RTC clock inside the module.
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Figure 3-3 Reference circuit of VRTC power 3.1.3 Power Output SC138 module has multiple power output channels, for peripheral circuit power supply. During application, capacitors of 33 pF and 10 pF can be paralleled to eliminate high-frequency interference. Table 3-4 Output power Pin Name Programmable Default Voltage (V) Range (V) Drive Current (mA) VREG_CAM0_DVDD_1P104 0.312–1.304 1.1 600 VREG_L9A_1P8 1.504–2.000 1.8 600 VREG_L12A_1P8 1.504–2.000 1.8 300 VREG_CAM_AF_2P8 1.5–3.4 2.
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Table 3-5 On/off control signals Pin Name Pin No. I/O KEY_PWR_N 123 DI Description Remarks Active low, can be used as on/off, restart, sleep/wakeup control. - 3.2.1.1 Startup After the VBAT is powered on, the trigger module starts up through pulling down the KEY_PWR_N pin for 2s to 8s.
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VB AT 2s t 8s KEY_PWR_N VREG_L9A_1P8 Other VREGs Figure 3-6 Startup timing sequence 3.2.1.2 Startup Normal shutdown: When the machine is turned on, pull down KEY_PWR_N pin for more than 0.5s, and then a checkbox will pop up in the display interface (choose shutdown or restart). Forced shutdown: Pull down KEY_PWR_N for 9s-15s, and then the system will be forced to shut down.
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sleeping status can be configured by software. When the modules are in the sleeping status, pull down KEY_PWR_N pins for 0.1s, and then the modules can be waked up. 3.2.2 Volume Control KEY_VOL_UP_N/KEY_VOL_DOWN_N pin is the volume increase/decrease key; for the circuit design of volume key, refer to the startup circuit design. Note: The parallel capacitance of volume key should not exceed 100 pF. 3.3 SPMI Interface None 3.4 USB Interface SC138 series modules support 1-channel USB 3.
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Table 3-7 Definition of pins of USB 3.0 interfaces Pin Name Pin No. I/O Description USB_SS_RX1_P 269 DI USB_SS_RX1_M 254 DI USB_SS_TX1_P 270 DO USB 3.1 differential data sending+ - USB_SS_TX1_M 255 DO USB 3.1 differential data sending- - USB_SS_RX0_P 173 DI USB_SS_RX0_M 175 DI USB_SS_TX0_P 172 DO USB 3.1 differential data sending+ - USB_SS_TX0_M 174 DO USB 3.1 differential data sending- - DP_AUX_N 263 I/O DP_AUX_P 274 I/O USB_PHY_PS 276 DI USB 3.
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C onnector M odule 10K Ω V B U S _D E T V BU S U S B _D M DM U S B _D P DP U S B _ID ID GND 4V GND Figure 3-8 USB 2.0 interface reference circuit design M odule G P IO C onnector DC-DC V BA T V B U S _D E T 10K Ω V BU S U S B _D M DM U S B _D P DP U S B _ID ID GND 4V GND Figure 3-9 USB 2.0 interface reference circuit design (with OTG functions) The reference circuit design of USB 3.
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10K Ω V B U S _D E T 4V M odule T ype C C onnector V BU S USB_DM DD+ USB_DP U S B _V C O N N APPS_I2C VBUS VC O N N CC1 F U S B 30 2 CC2 I2C CC1 CC2 USB_SS_TX0_P USB_SS_TX0_M S STX P1 S STX N 1 S SR X P1 S SR X N 1 USB_SS_RX0_P USB_SS_RX0_M USB_SS_TX1_P USB_SS_TX1_M USB_SS_RX1_P USB_SS_RX1_M GND E SD S STX P2 S STX N 2 S SR X P2 S SR X N 2 GND Figure 3-10 USB 3.
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speed differential routing. 2) The differential impedance control is made properly, 90 Ω + - 10%, and the length difference of differential line is controlled within 0.7 mm. 3) The stray capacitance of ESD device must be less than 0.5 pF. 3.5 UART SC138 module has three UART interfaces, which are all in voltage domain of 1.8 V. The pin definition is as follows: Table 3-8 Definition of pins of UART interfaces Pin Name Pin No.
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C onverter V D D _1V 8 VC CA VC CB 0.1uF V D D _M C U 0.1uF OE GND U A R T _T X D A1 B1 M C U _T X D U A R T _R X D A2 B2 M C U _R X D U A R T _C T S A3 B3 M C U _C T S A4 B4 U A R T _R T S M C U _R T S Figure 3-11 Reference circuit of level conversion 3.6 SPI SC138 series modules provide a set of SPI interfaces and only support the main device mode. The pin definition is shown in the following figure: Table 3-9 Definition of pins of SPI interfaces Pin Name Pin No.
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Pin Name Pin No.
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3.8 SDIO Interface SC138 supports 1-channel SDIO interfaces, and the pin definition is shown in the following table: Table 3-11 Definition of pins of SDIO interfaces Pin No.
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1) VREG_L22A_2P96 is an external drive power supply for SD card, which can provide about 600 mA current with the line width of 1 mm. 2) The SD_CARD_DET_N pull-up resistor is connected to VREG_L9A_1P8 power supply. 3) SDIO is a high-speed digital signal line and needs to be shielded. 4) SDIO data lines are processed to be of equal length. 3.9 GPIO SC138 series modules have abundant GPIO resources, the interface level is 1.
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Pin Name Pin No. Reset State Interrupt Function GPIO_113 212 B-PD:nppukp NO GPIO_117 218 B-PD:nppukp YES GPIO_119 219 B-PD:nppukp NO PM6125_GPIO_1 249 B-PD:nppukp YES PM6125_GPIO_2 245 B-PD:nppukp YES PM6125_GPIO_4 243 B-PD:nppukp YES Note: B: Bidirectional digits with CMOS input. H: High voltage resistance. NP: pdpukp = no pull by default, with programmable options after the colon (:). PD: nppukp = pull-down by default, with programmable options after the colon (:).
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Pin Name Pin No. I/O Description Remarks CAM0_I2C_SCL 84 OD Camera I2C clock They are special CAM0_I2C_SDA 85 OD Camera I2C data for the camera and CAM2_SCL 206 OD Camera I2C clock cannot be used on CAM2_SDA 208 OD Camera I2C data other devices. APPS_I2C_SCL 268 OD I2C clock Need be Pulled-up APPS_I2C_SDA 267 OD I2C data line too, when unused Note: When mounting multiple peripherals on the I2C channel, please ensure the uniqueness of each peripheral address.
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Table 3-15 I2S interface definition I2S Interface GPIO_125/I2S1_SCK 247 DO I2S serial clock - GPIO_126/I2S1_WS 238 DO I2S frame clock - GPIO_127/I2S1_DATA0 239 DO I2S data 0 - GPIO_128/I2S1_DATA1 240 DO I2S data 1 Boot Config, Flash GPIO_118/MCLK2 251 DO I2S system clock Memory type configure 3.13 Battery Power Supply Interface None 3.14 Motor Drive Interface None 3.
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Pin Name Pin No.
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Figure 3-14 LCM reference circuit LCM design considerations: 1) MIPI is a high-speed signal line. It is recommended to connect a common mode choke in series near the LCD connector to improve the electromagnetic radiation interference of the circuit. 2) MIPI route is recommended to be placed on the inner layer, and be surrounded by grounding lines in a three-dimensional manner. 3) The MIPI signal line needs to be controlled by a differential impedance of 100 Ω, with an error of ±10%.
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The TP reference circuit is shown in the following figure: V R E G _L9A _1P 8 V R E G _3P 0 10K 2.2K 2.2K TP M odule VDD TS_I2C_SCL SCL TS_I2C_SDA SDA R ES E T T S _R S T T S _IN T _N IN T 2.2uF 100nF Figure 3-15 TP reference circuit 3.17 Camera The video input interface of the SC138 series module is based on the MIPI_CSI standard, and can support 3 (4+4+4-Lane) or 4 (4+4+2+1-Lane) cameras. It is equipped with 3 cameras by default. Support 21 MP pixel camera at maximum.
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4-Lane+4-Lane+4-Lane (Default Pin Name Pin No.
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4-Lane+4-Lane+4-Lane (Default Pin Name Pin No. I/O MIPI_CSI1_LANE3_N 261 AI/AO Camera 1 MIPI Lane3- CAM2_MCLK 213 DO Camera 2 MCLK signal - CAM2_RST_N 214 DO Camera 2 reset signal - CAM2_PWD_N 215 DO Camera 2 PWD signal - IOVDD_1.8V_EN 210 DO IOVDD power enabling signal - CAM1_MCLK/GPIO_44 101 DO Camera 3 MCLK signal Configuration) (Configurable) 3.17.
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VREG_CAM_AF_2P8 V R E G _L12A _1P 8 VREG_CAM1_2_DVDD_1P104 VREG_CAM1_2_AVDD_2P8 V R E G _L12A _1P 8 DOVDD 2.2K 2.
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V R E G _L12A _1P 8 VREG_CAM0_DVDD_1P104 VREG_CAM0_AVDD_2P8 DOVDD 2.2K Module 2.2K V R E G _L12A _1P 8 DVDD AVDD CAM0_CLK PWD CAM0_RST_N RST CAM2_I2C_SCL SCL CAM2_I2C_SDA SDA MIPI_CSI0_CLK_P CLK_P EM I CLK_N MIPI_CSI0_CLK_N MIPI_CSI0_LAN0_P DAT0_P EM I MIPI_CSI0_LAN0_N DAT0_N MIPI_CSI0_LAN1_P DAT1_P EM I MIPI_CSI0_LAN1_N 1uF 100nF 10uF 100nF 1uF 10uF DAT1_N CAM Connector C A M C onnector MCLK CAM0_PWD_N Figure 3-18 Reference circuit for camera 3 3.17.
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V R E G _L12A _1P 8 VREG_CAM0_DVDD_1P104 VREG_CAM0_AVDD_2P8 DOVDD 2.2K DVDD AVDD CAM3_CLK MCLK CAM3_PWD_N PWD CAM3_RST_N RST CAM_I2C_SCL SCL CAM_I2C_SDA SDA MIPI_CSI0_LAN3_P CLK_P EM I CLK_N MIPI_CSI0_LAN3_N MIPI_CSI0_LAN2_P DAT0_P EM I MIPI_CSI0_LAN2_N C A M C onnector Module 2.2K V R E G _L12A _1P 8 1uF 100nF 10uF 100nF 1uF 10uF DAT0_N Figure 3-19 Reference circuit for camera 4 3.17.5 Design Considerations MIPI_CSI is a high-speed data line.
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width. 8) The total stray capacitance of devices on MIPI differential signal line should not exceed 1pF. Other signal line design considerations: 1) CAM_CLK is a high-speed clock signal and needs to be surrounded by grounding lines in a threedimensional manner. 2) If the front and rear cameras share I2C, the I2C addresses of the two cameras should be confirmed that there is no conflict. 3) The analog voltage AVDD route should be away from the interference source to avoid the power noise.
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3.19 Audio 3.19.1 Audio Interface Definition SC138 series modules support analog audio interfaces with 3 inputs and 3 outputs, and the pin definition is shown in the following table: Table 3-20 Audio interface definition Pin Name Pin No.
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Pin Name Pin No. I/O Description Remarks input+ default, and grounding Audio interface design considerations: 1) There is a MIC bias circuit in the SC138 module, so no external addition is required. 2) SPK is equipped with Class-D power amplifier, so no external power amplifier is allowed. It is recommended to connect an 8 Ω loudspeaker. The route width should meet the requirements of rated power.
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Figure 3-20 Microphone circuit design 3.19.3 Handset Circuit Design 33 pF M odule 10 0pF CDC_EAR_P 33pF CDC_EAR_N Figure 3-21 Handset circuit design 3.19.4 Earphone Interface Circuit Design Module 33pF MIC2_P CDC_HPH_L CDC_HPH_R HPH_DET 0R 0R 33 pF 33 pF CDC_HPH_REF 0R Figure 3-22 Earphone interface circuit design Note: Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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For the ESD protection device of the earphone interface, use the bidirectional TVS tubes. 3.19.5 Speaker Circuit Design M odule S P K R _D R V _P 39 pF 39 pF S P K R _D R V _N Figure 3-23 Speaker circuit design 3.20 Forced Downloading Interface Design SC138 series modules provide FORCE_USB_BOOT pins as emergency downloading interfaces. Shortcircuit the USB_FORCE_BOOT and VREG_L9_1P8 pins when starting up, and the module can enter the emergency downloading mode.
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3.20.1Circuit Reference Design When using SC138 series modules, it is necessary to connect the antenna pins and the RF connector or antenna feedpoint on the main board through the RF route. Microstrip line is recommended for the RF route, the insertion loss is controlled within 0.2 dB, and the impedance is controlled within 50 Ω. A π-type circuit is reserved between the module and the antenna connector (or feedpoint) for antenna commissioning.
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Table 3-22 WIFI/BT band Mode Frequency Unit 2402–2482 MHz 5170–5835 MHz 2402–2480 MHz WIFI BT5.0 3.21.2Circuit Reference Design WIFI/BT antenna connection reference circuit is shown in the following figure. M odule W IFI/B T _A ntenna 0R A N T_W IFI/B T NC NC Figure 3-26 WIFI/BT reference circuit 3.22 GNSS Antenna GNSS supports GPS, GLONASS and Beidou. Table 3-23 Definition of GNSS antenna interface Pin Name Pin No.
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Table 3-24 GNSS band Mode Frequency Band Unit GPS 1575.42±1.023 MHz GLONASS 1597.42-1605.8 MHz BeiDou 1561.098±2.046 MHz 3.22.2Circuit Reference Design The LNA is built into the SC138 series module, and the passive antenna is selected in the whole machine design. Microstrip line is recommended for the GNSS RF routing, the insertion loss is controlled within 0.2 dB, and the impedance is controlled within 50 Ω.
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Figure 3-28-2 Reference circuit of GNSS active antenna The power supply of the active antenna is fed by 56 nH inductance from the signal line of the antenna. The common active antenna supplies power for 3.3 V–5.0 V. The power consumption of active antenna is very small, but the power supply is required to be stable and clean. It is recommended to use LDO with high performance to power the antenna. The gain of active antenna is required to be < 17 dB.
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SC138SC138 Series Modules Antenna Requirements Input impedance (Ω): 50 Polarization type: vertical direction Insertion loss: < 1 dB (0.7-1GHz) Insertion loss: < 1.5 dB (1.4-2.2GHz) Insertion loss: < 2 dB (2.3-2.
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4 RF PCB Layout Design Guide For user PCB, the characteristic impedance of all RF signal lines shall be controlled at 50 Ω. In general, the impedance of the RF signal line is determined by the dielectric constant of the material, the routing width (W), the ground clearance (S), and the height of the reference ground plane (H). The characteristic impedance of PCB is usually controlled by microstrip line and coplanar waveguide.
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Figure 4-3 Coplanar waveguide structure of four-layer PCB (reference ground layer 3) Figure 4-4 Coplanar waveguide structure of four-layer PCB (reference ground layer 4) In the circuit design of RF antenna interface, in order to ensure the good performance and ALT of RF signal, the following design principles are recommended in the circuit design:  The impedance simulation calculation tools shall be used to accurately control the 50 Ω impedance of the RF signal line.
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 The reference ground plane of RF signal line shall be complete; adding a certain amount of ground holes around the signal line and the reference ground can help improve the RF performance; the distance between the ground hole and the signal line shall be at least twice the line width (2 * W). Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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5 WIFI and Bluetooth 5.1 WIFI Overview SC138SC138 series modules support 2.4G and 5G WLAN wireless communication, and support the types of 802.11a, 802.11b, 802.11g, 802.11n and 802.11ac, with the highest rate of 433 Mbps. Characteristics are described as follows:  Support Wake-on-WLAN (WoWLAN)  Support ad hoc mode  Support WAPI  Support AP mode  Support Wi-Fi Direct  Support MCS 0-7 for HT20 and HT40 (if the 2.
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Frequency Mode Date Rate Bandwidth (MHz) TX Power (dBm) MCS7 40 12.0±3 6Mbs 20 19.0±3 54Mbps 20 16.0±3 MCS0 20 18.0±3 MCS7 20 15.0±3 MCS0 40 17.0±3 MCS7 40 14.0±3 MCS0 20 17.0±3 MCS8 20 14.0±3 MCS0 40 16.0±3 MCS9 40 13.0±3 MCS0 80 15.0±3 MCS9 80 12.0±3 802.11a 802.11n 5G 802.
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Frequency Mode Date Rate Bandwidth (MHz) MCS0 20 MCS7 20 MCS0 40 MCS7 40 MCS0 20 MCS8 20 MCS0 40 MCS9 40 MCS0 80 MCS9 80 802.11n 802.11n 802.11ac ） Sensitivity(dBm) 2 -90.0 -71.0 -88.0 -68.0 -90.0 -69.0 -87.0 -65.0 -85.0 -62.0 Note: 2) The sensitivity here is typical. 5.3 Bluetooth Overview SC138SC138 series modules support BT5.0 (BR/EDR+BLE) specifications, and the modulation mode supports GFSK; the channel bandwidth of 8-DPSK and π/4-DQPSK.
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Table 5-3 BT rate and version information Version Date Rate Throughput Note BT1.2 1Mbit/s > 80Kbit/s - BT2.0+EDR 3Mbit/s > 80Kbit/s - BT3.0+HS 24Mbit/s For details, see 3.0+HS - BT5.0 LE 24Mbit/s For details, see 5.0 LE - 5.4 Bluetooth Performance Indicators Test conditions: supply voltage 3.8 V, ambient temperature 25ºC. Table 5-4 BT performance indicators Type DH-5 2-DH5 3-DH5 BLE Unit Transmitter 11±2.5 9±2.5 8±2.5 6±2.
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6 GNSS 6.1 Overview SC138SC138 series intelligent modules support GPS, GLONASS and Beidou and other positioning systems. LNA is embedded in the module, which can effectively improve the sensitivity of GNSS. 6.2 Performance Index Test conditions: supply voltage 3.8 V, ambient temperature 25ºC.
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7 Electrical, ALT and RF Performance 7.1 Recommended Parameters Table 7-1 recommended parameters Parameter Min Normal Max Unit VBAT 3.5 3.8 4.2 V USB_IN_DET 4.75 5 5.25 V VRTC 2.0 3.0 3.25 V -30 25 75 ºC -40 25 85 ºC Operating Temperature Storage Temperature 7.2 Operating Current Test conditions: supply voltage 3.8 V, ambient temperature 25ºC. Table 7-2 SC138-NA operating current Parameter Description Condition Type Unit Ioff Power Off Power Off 50 uA WCDMA DRX=8 4.
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Parameter Description Condition Type Band7@max power(10MHz,1RB) 720 Band12@max power(10MHz,1RB) 650 Band13@max power(10MHz,1RB) 560 Band17@max power(10MHz,1RB) 680 Band25@max power(10MHz,1RB) 680 TDD data Band41@max power(10MHz,1RB) 430 RMS Current Band48@max power(10MHz,1RB) 340 Unit 7.
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8 Structural Specification 8.1 Product Appearance 8.2 Structure Size 8.3 Reference PCB Bonding Pad Design For details of recommended design of PCB bonding pad and corresponding steel mesh, see FIBOCOM SC138 Series SMT Design Guide. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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9 Production and Storage 9.1 SMT Patch For details of SMT production process parameters and related requirements, see FIBOCOM SC138 Series SMT Design Guide. 9.2 Packaging and Storage For details of packing and storage, see FIBOCOM SC138 Series SMT Design Guide. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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Appendix A Abbreviations Table A-1 Abbreviations Abbreviation Meaning AMR Adaptive Multi-rate bps Bits Per Second CS Coding Scheme DRX Discontinuous Reception FDD Frequency Division Duplexing GMSK Gaussian Minimum Shift Keying HSDPA High Speed Down Link Packet Access IMEI International Mobile Equipment Identity Imax Maximum Load Current LED Light Emitting Diode LSB Least Significant Bit LTE Long Term Evolution CA Carrier Aggregation DLCA Downlink Carrier Aggregation SCell Seco
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Abbreviation Meaning RHCP Right Hand Circularly PolarizedRMS RMS Root Mean Square RTC Real Time Clock Rx Receive SMS Short Message Service TDMA Time Division Multiple Access TE Terminal Equipment TX Transmitting Direction TDD Time Division Duplexing UART Universal Asynchronous Receiver & Transmitter UMTS Universal Mobile Telecommunications System URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module USSD Unstructured Supplementary Service Data Vmax Maximum
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Appendix B GPRS Coding Scheme Table B-1 GPRS coding scheme Coding Mode CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.4 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All rights reserved.
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Appendix C GPRS Multi-slot In the GPRS specification, 29 kinds of GPRS multi-slot modes are defined for mobile stations. The multislot class defines the maximum rate of uplink and downlink. Expressed as 3 + 1 or 2 + 2, the first number represents the number of downlink slots, and the second number represents the number of uplink slots.
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Appendix D EDGE Modulation and Coding Mode Table D-1 EDGE modulation and coding mode Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1 GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2 GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3 GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4 GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.6kbps 35.2kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.8kbps 29.6kbps 59.2kbps MCS-4 GMSK C 17.6kbps 35.