FIBOCOM SU806-LA Hardware Guide Version: V2.0.
Copyright Copyright ©2021 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or transmit the document in any form. Notice The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide.
End Product Labeling When the module is installed in the host device, the FCC/IC ID label must be visible through a window on the final device or it must be visible when an access panel, door or cover is easily re-moved. If not, a second label must be placed on the outside of the final device that contains the following text: “Contains FCC ID: ZMOSU806LA”. The FCC ID can be used only when all FCC compliance requirements are met.
List of applicable FCC rules This module has been tested and found to comply with part 15C, part 22, part 24, part 27, part 90 requirements for Modular Approval. The modular transmitter is only FCC authorized for the specific rule parts (i.e., FCC transmitter rules) listed on the grant, and that the host product manufacturer is responsible for compliance to any other FCC rules that apply to the host not covered by the modular transmitter grant of certification.
1 Introduction 1.1 Instruction This document describes the electrical characteristics, RF performance, structure size, application environment, etc. of SU806 series module. With the assistance of the document and other instructions, the developers can quickly understand the hardware functions of the SU806 series module and develop products. 1.2 Reference Standards The design of product refers to the following standards: ⚫ 3GPP TS 51.010-1 V10.5.
⚫ Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0+EDR/2.1/2.1+EDR/3.0/3.0+HS, August 6, 2009 ⚫ Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.0, December 15, 2009 1.3 Related Document FIBOCOM Sx806 Series SMT Design Guide Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
2 Product Overview 2.1 Product Introduction SU806 series smart module integrates core components such as Baseband, eMCP, PMU, Transceiver, PA; it supports long distance multi-mode communication such as FDD/TDD-LTE, WCDMA, GSM and WIFI/BT short-distance radio transmission technology, as well as GNSS wireless positioning technology. SU806 series module is embedded with Android operating system and support various interfaces such as MIPI/USB/UART/SPI/I2C.
Performance Description Power Supply DC:3.5~4.2V, typical:3.8V Application processor Quad-core ARM® CortexTM A53 MP processor, up to 1.4GHz Memory 8GB e.MMC+8Gb LPDDR3 16GB e.
Performance Description 802.11g, 802.11n, the maximum rate up to 72.2Mbps Bluetooth BT4.
Performance I2C interface Description Multiple I2C interfaces, can be used for peripherals such as TP, camera, and sensor ADC interface One universal 12bits ADC RTC Support Antenna interface MAIN antenna, DRX antenna, GNSS antenna, WIFI/BT antenna Dimension: 40.5mm×40.5mm×2.8mm Physical characteristics Encapsulation: 146 LCC pin + 116 LGA pin Weight: about 9.
A N T _M A IN TX M SAW SAW SAW LN A SAW D Rx PRx LP D D R 3 S D R AM eM M C Tx P ow er T ransceiver PRx V B AT 26M XO V R TC ADC S w itch D uplex PA A U D IO A N T _W IFI/B T A N T _G N S S A N T _D IV PM U C ontrol A ir R ES E T In terface M em ory B aseband PW RKEY M ultim edia LC M TP C AM C onnectivity I2 C SPI U AR T (U )S IM S D IO G P IO U SB V oL key Figure 2-1 Functional block diagram Reproduction forbidden without Fibocom Wireless Inc.
2.4 Pin Definition 2.4.1 Pin Assignment Figure 2-2 Pin assignment (top view) Note: “NC” represent No Connect, the pin of this position is reserved and does not need to be connected. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
2.4.
Pin Name Pin Number I/O Functional Description Note Output for camera analog VDDCAMA 129 PO VDDCAMCORE 151 PO Output for camera digital power - VDD2V8 228 PO 2.8V voltage output - VIB_DRV_N 28 PO Vibrator drive output power, 2.
Pin Name Pin Number I/O Functional Description Note KEY_RESIN_N)reset and one key(KEY_PWR_ON) reset CBL_PWR_N Power on key 2, just have 261 DI UIM2_DATA 20 I/O (U)SIM card 2 data - UIM2_CLK 19 DO (U)SIM card 2 clock - UIM2_RST 18 DO (U)SIM card 2 reset - power on function Active low (U)SIM card interface UIM2_DET 17 DI (U)SIM card 2 hot plug detection Disabled by default, cannot used as general GPIO UIM1_DATA 25 I/O (U)SIM card 1 data - UIM1_CLK 24 DO (U)SIM card 1 cl
Pin Name Pin Number I/O Functional Description Note SENSOR_I2C_SDA 92 I/O I2C data For sensor by default TP_I2C_SCL 47 DO I2C clock For touch panel by default TP_I2C_SDA 48 I/O I2C data For touch panel by default CAM_I2C_SCL0 83 DO I2C clock CAM_I2C_SDA0 84 I/O I2C data CAM_I2C_SCL1 239 DO I2C clock CAM_I2C_SDA1 240 I/O I2C data USB_VBUS 141,142 PI USB 5V input - USB_DP 14 AI/AO USB HS data+ - USB_DM 13 AI/AO USB HS data- - USB_ID 16 DI USB OTG detection
Pin Name Pin Number I/O Functional Description Note SPI_CS 117 DO SPI chip selects - SPI_MISO 118 DI SPI master input slave output - SPI_MOSI 119 DO SPI master output slave input - MIPI_DSI0_CLK_N 52 AO MIPI display serial interface - MIPI_DSI0_CLK_P 53 AO clock - MIPI_DSI0_LN0_N 54 AO - MIPI_DSI0_ LN0_P 55 AO - MIPI_DSI0_ LN1_N 56 AO - MIPI_DSI0_ LN1_P 57 AO MIPI display serial interface - MIPI_DSI0_LN2_N 58 AO lane - MIPI_DSI0_LN2_P 59 AO - MIPI_DSI0
Pin Name Pin Number I/O Functional Description interface lane Note MIPI_CSI0_LN0_N 231 AI MIPI_CSI0_LN1_P 156 AI MIPI_CSI0_LN1_N 232 AI MIPI_CSI0_LN2_P 157 AI MIPI_CSI0_LN2_N 233 AI MIPI_CSI0_LN3_P 158 AI MIPI_CSI0_LN3_N 234 AI MCAM_MCLK 74 DO Rear camera master clock - MCAM_RST 79 DO Rear camera reset signal - MCAM_PWDN 80 DO Rear camera power down - MIPI_CSI1_CLK_N 63 AI MIPI front camera serial - MIPI_CSI1_CLK_P 64 AI interface clock - MIPI_CSI1_LN0_N 6
Pin Name Pin I/O Functional Description Note 236 DO Depth camera power down - SPK_P 10 AO Speaker amp + output - SPK_M 11 AO Speaker amp - output - EAR_P 8 AO Earpiece PA + output - EAR_M 9 AO Earpiece PA - output - HPH_L 138 AO HPH_GND 137 - HPH_R 136 AO HPH_DET 139 AI Headset detection - MIC2_P 6 AI Headset MIC difference input + - MIC1_M 5 AI MIC1 difference input - - MIC1_P 4 AI MIC1 difference input + - MIC_BIAS1 219 AO MIC bias1 - MIC3_P
Pin Name Pin Number I/O Functional Description Note MAG_RST 109 DO Magnetic sensor reset - ACCL_INT 110 DI Accelerometer sensor interrupt - ADC 128 AI ADC detection - LED_B 194 AI RGB LED input2 - LED_G 195 AI RGB LED input1 - LED_R 196 AI RGB LED input0 - CHG_EN 210 AO Charge enable - Other interface The PIN260 is NC which ADC4_BAT_ID 260 AI BAT_ID detection product models support internal charging NFC_CLK 256 DO NFC clock Reserved NFC_DWL_REQ 257 DI NF
Pin Name Pin Number I/O Functional Description Note GPIO_32 112 I/O INPUT (WPD) GPIO_89 113 I/O OUTPUT GPIO_122 115 I/O WPD GPIO_139 123 I/O INPUT (WPU) GPIO_140 124 I/O INPUT (WPU) GPIO_88 153 I/O INPUT (WPU) GPIO_30 159 I/O INPUT (WPD) GPIO_29 183 I/O INPUT (WPD) GPIO_27 187 I/O INPUT (WPD) GPIO_85 202 I/O OUTPUT GPIO_154 203 I/O INPUT (WPD) GPIO_155 205 I/O INPUT (WPD) GPIO_28 206 I/O INPUT (WPD) INPUT (WPD) GPIO_24 207 I/O Boot configuration do
Pin Name NC Pin Number I/O Functional Description 154, 191, 197, 199, 204, 222 to 224, 247 to 249, 255 Note Keep floating Note: H: High-voltage tolerant L: Low-voltage tolerant Hiz: High impedance WPU: Weak pull up WPD: Weak pull down The GPIOs with “WPU” aren’t recommended as the enable control of default highly efficient devices. For example, backlight enable of LCM and audio amplifier enable. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
3 Application Interface 3.1 Power Supply The SU806 series module provides four VBAT pins for connecting to external power supply source. The input range of power is 3.5V to 4.2V and the recommended value is 3.8V. The performance of the power supply such as its load capacity, ripple etc. will directly affect the operating performance and stability of the module.
The reference design of power supply is shown as the following figure: VBAT M odule + 220uF 220uF 1uF 100nF 39pF 33pF 18pF 8.2pF 6.
VRTC input voltage - 3.0 - V VRTC input current - 40 - uA The reference design of VRTC pin powered by external power source is shown the following figure: M odule V R TC + C oin cell Figure 3-3 VRTC reference design 3.1.3 Power Output The SU806 series module provides multiple power outputs for peripheral circuits. It is recommended to connect 33pF and 10pF capacitors in parallel with every power to avoid high frequency interference effectively.
VDDCAMCORE 1.00625-1.4 1.2 400 VDD2V8 1.8-3.3 2.8 200 VIB_DRV_N 1.8-3.3 3.3 100 3.2 Control Signal 3.2.1 Power on/off SU806 series module provides one-way power on/off control signal to module’s power on/off, restart and sleep/wake up. Its pin definition is shown as follow table: Table 3-5 Power on/off signal Pin Pin Name Number I/O KEY_PWR_ON 114 DI CBL_PWR_N 261 DI 3.2.1.
K E Y _P W R _O N 3s≤t≤6s 100pF 10K 47K Figure 3-5 OC drive power on reference design The power on timing is shown as follows: VB AT 3.5s≤t≤6s KEY_PWR_ON VDD1V85 Other Powers Figure 3-6 Power on timing 3.2.1.2 Power off Normal power off: when module in operating mode, pull down KEY_PWR_ON pin 0.6s~6s, user interface will display selection box (select power off or restart).
enter sleep mode. When module in sleep mode, pull down KEY_PWR_ON pin 0.1s~0.5s and then release it, module can be waked up. 3.2.2 Reset Support one key (KEY_PWR_ON) reset and two key (KEY_PWR_ON & KEY_RESIN_N) reset; and two key reset mode is default. One key (KEY_PWR_ON) reset: when module in operating mode, pull down KEY_PWR_ON pin 0.6s~6s, user interface will display selection box (select power off or restart); pull down KEY_PWR_ON pin 7s~10s module will be forced reset.
Table 3-6 USB 2.0 pin definition Pin Pin Name Number I/O Description Note USB_VBUS 141,142 PI USB VBUS 5V input - USB_DP 14 AI/AO USB HS data + - USB_DM 13 AI/AO USB HS data - - USB_ID 16 DI USB OTG detection - The reference design of USB 2.0 is show as follow figure: Connector Module VBUS USB_DM DM USB_DP DP USB_ID ID 1uF USB_VBUS GND Figure 3-8 USB 2.0 reference design Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
Module GPIO Connector DC-DC VBAT VBUS USB_DM DM USB_DP DP USB_ID ID 1uF USB_VBUS GND Figure 3-9 USB 2.0 reference design (with OTG function) Note: 1) Please choose junction capacitor less than 1pF for ESD protection device of USB_DP/DM 2) USB_DP and USB_DM are high-speed differential signal. The highest transmission rate is 480Mbps.
UART 3.4 SU806 series module defines three UART ports,all are 1.8V voltage domain ,the function of UART2 has not achieve at present.
The other level translator circuit is shown as Figure 3-11, The rest input and output circuit design of dotted line please refer to solid line part, but pay attention to signal connection direction. Figure 3-11 Level shift reference design 2 3.
Table 3-10 (U)SIM pin definition Pin Pin Name Number I/O Description Note UIM1_DATA 25 I/O (U)SIM 1 data signal - UIM1_CLK 24 DO (U)SIM 1 clock signal - UIM1_RST 23 DO (U)SIM 1 reset signal - UIM1_DET 22 DI (U)SIM 1 plug detection UIM2_DATA 20 I/O (U)SIM 2 data - UIM2_CLK 19 DO (U)SIM 2 clock - UIM2_RST 18 DO (U)SIM 2 reset - UIM2_DET 17 DI (U)SIM 2 plug detection VDDSIM1 26 PO (U)SIM 1 power supply - VDDSIM2 21 PO (U)SIM 2 power supply - Disabled by def
Figure 3-12 (U)SIM reference design (U)SIM card design notice: 1) The length from the (U)SIM card holder to module should less than 100mm. 2) The layout and routing of the (U)SIM card must be kept away from EMI interference sources such as RF antenna and digital switch power. 3) The decoupling capacitors of the (U)SIM card signal and the ESD device should be placed close to the card holder. 3.7 SDIO SU806 series module supports one SDIO interface.
VDDSDCORE VDD1V85 100MHz_120R 100nF 4.7uF 100K Module Connector VDD 0R SD_DATA3 DAT3 0R SD_DATA2 DAT2 0R DAT1 SD_DATA1 0R SD_DATA0 DAT0 0R SD_CLK CLK 0R SD_CMD CMD 22R SD_DET DETECTIVE NC NC NC NC NC NC Figure 3-13 SDIO reference design SDIO design notice: 1) VDDSDCORE is the SD card peripheral driving power and can provide about 400mA current. SD3.0 need external LDO with power driver ability more than 800mA.
Interrupt Pin Name Pin Number H/L/Hiz After Reset After Reset GPIO_131 101 L INPUT(WPD) YES GPIO_130 102 L INPUT(WPD) YES GPIO_133 103 L INPUT(WPD) YES GPIO_132 104 L INPUT(WPD) YES GPIO_121 105 L OUTPUT YES GPIO_138 106 H INPUT(WPU) YES GPIO_91 108 L INPUT(WPD) YES GPIO_32 112 L INPUT(WPD) YES GPIO_89 113 L OUTPUT YES GPIO_122 115 Hiz WPD YES GPIO_139 123 H INPUT(WPU) YES GPIO_140 124 H INPUT(WPU) YES GPIO_88 153 H INPUT(WPU) YES GPIO_30
Interrupt Pin Name Pin Number H/L/Hiz After Reset After Reset GPIO_11 241 L INPUT(WPD) YES GPIO_7 242 L INPUT(WPD) YES GPIO_143 243 H INPUT(WPU) YES GPIO_10 244 L INPUT(WPD) YES GPIO_141 97 H INPUT(WPU) YES GPIO_26 252 L INPUT(WPD) YES GPIO_22 253 L INPUT(WPD) YES GPIO_23 254 L INPUT(WPD) YES Function Note: H: High-voltage tolerant L: Low-voltage tolerant Hiz: High impedance WPU: Weak pull up WPD: Weak pull down 3.
TP_I2C_SDA 48 I/O I2C data For touch panel by default CAM_I2C_SCL0 83 DO I2C clock For rear/front camera by default CAM_I2C_SDA0 84 I/O I2C data For rear/front camera by default CAM_I2C_SCL1 239 DO I2C clock For depth camera by default CAM_I2C_SDA1 240 I/O I2C data For depth camera by default Note: When I2C has more than one peripheral, please ensure the uniqueness of every peripheral address. 3.
Detection voltage range is 0.1V~1.2V with ADC 128 AI ADC detection maximum 50mV accuracy and 0.1V~3.0V with maximum 150mV test accuracy, software configurable ADC4_BAT _ID 260 AI BAT_ID detection The PIN260 is NC which product models support internal charging 3.12 Battery Power Supply Interface SU806 series module just support circuit modes coulomb counter fuel gauge, if use coulomb counter IC externally, please connect SENSE_P and SENSE_N pin to GND.
Note: Trace routing of SENSE_P and SENSE_N should follow differential rule. The impedance of VBAT_SNS pin varies with the use scenario, if VBAT_SNS not connect with battery directly, recommend add isolators between VBAT_SNS pin and battery. 3.13 Charge Enable Interface Table 3-17 Charge enable interface pin definition Pin Name CHG_EN Pin Number 210 I/O Description Note AO Charge enable output - 3.
Pin Name Pin Number I/O Description Note MIPI_DSI0_LN0_N 54 AO MIPI display serial interface Lane0 - - MIPI_DSI0_LN0_P 55 AO MIPI display serial interface Lane0 + - MIPI_DSI0_LN1_N 56 AO MIPI display serial interface Lane 1- - MIPI_DSI0_LN1_P 57 AO MIPI display serial interface Lane 1+ - MIPI_DSI0_LN2_N 58 AO MIPI display serial interface Lane 2- - MIPI_DSI0_LN2_P 59 AO MIPI display serial interface Lane 2+ - MIPI_DSI0_LN3_N 60 AO MIPI display serial interface Lane 3 -
VDD1V85 100nF 100nF 100nF 2.
Pin Pin Name Number Length (mm) MIPI_DSI0_CLK_P 53 63.00332 MIPI_DSI0_LN0_N 54 62.71304 MIPI_DSI0_LN0_P 55 62.44077 MIPI_DSI0_LN1_N 56 62.22446 Length Difference (DP-DM) mm -0.27227 0.32383 MIPI_DSI0_LN1_P 57 62.54829 MIPI_DSI0_LN2_N 58 62.8235 0.1031 MIPI_DSI0_LN2_P 59 62.9266 MIPI_DSI0_LN3_N 60 63.84148 -0.39457 MIPI_DSI0_LN3_P 61 63.44691 3.
VDD2V8 VDD1V85 10K NC NC TP Module VDD TS_I2C_SCL SCL TS_I2C_SDA SDA RESET TP_RST TP_INT INT 2.2uF 100nF Figure 3-16 TP reference design 3.17 Camera The camera interface is based on the MIPI_CSI standard and can support three (4-lane+2-lane+1-lane) cameras, maximum 13MP. The pin definition of camera interface is shown in the following table: Table 3-22 Camera interface pin definition Pin Pin Name Number I/O 4-Lane+2-Lane+1-Lane Note VDD1V8 125 PO DOVDD power supply, 1.
Pin Pin Name Number I/O 4-Lane+2-Lane+1-Lane Note MIPI_CSI0_LN1_N 232 AI MIPI rear camera serial interface lane 1- - MIPI_CSI0_LN2_P 157 AI MIPI rear camera serial interface lane 2+ - MIPI_CSI0_LN2_N 233 AI MIPI rear camera serial interface lane 2- - MIPI_CSI0_LN3_P 158 AI MIPI rear camera serial interface lane3+ - MIPI_CSI0_LN3_N 234 AI MIPI rear camera serial interface lane 3- - MCAM_MCLK 74 DO Rear camera master clock - MCAM_RST 79 DO Rear camera reset - MCAM_PWDN
Pin Pin Name Number I/O 4-Lane+2-Lane+1-Lane Note MIPI_CSI1_LN2_P 73 AI MIPI depth camera serial interface lane 0 + - DCAM_MCLK 238 DO Depth camera master clock - DCAM_RST 237 DO Depth camera reset - DCAM_PWDN 236 DO Depth camera power down - CAM_I2C_SCL1 239 DO Front/depth camera I2C clock - CAM_I2C_SDA1 240 I/O Front/depth camera I2C data - 3.17.
VDD1V8 VD DC AM C O R E VD DC AM A V D D 1V 85 NC NC DVDD Module DOVDD MCLK SCAM_PWDN PWD SCAM_RST RST CAM_I2C_SCL1 SCL CAM_I2C_SDA1 SDA MIPI_CSI1_CLK_P CLK_P EM I CLK_N MIPI_CSI1_CLK_N MIPI_CSI1_LN0_P DAT0_P EM I MIPI_CSI1_LN0_N DAT0_N MIPI_CSI1_LN1_P DAT1_P EM I MIPI_CSI1_LN1_N 100nF 1uF 10uF 100nF 10uF DAT1_N CAM Connector C A M C onnector AVDD SCAM_MCLK Figure 3-18 Front camera reference design 3.17.
near the LCD connector to reduce the electromagnetic interference of the circuit. 2) MIPI routing is recommended to be in the inner layer, with three-dimensional grounding; 3) The MIPI signal needs to be controlled with a differential impedance of 100Ω tolerance ±10%; 4) The total length of the trace must ≤ 70mm, VIAs ≤ 4; 5) The intra lane match of MIPI differential pair signal must ≤ 0.5 mm; 6) The inter lane match of MIPI signal must ≤ 2 mm; 7) It is recommended that the space of intra lane should be 1.
Pin Pin Name Length (mm) Number MIPI_CSI1_CLK_P 64 10.74214 MIPI_CSI1_CLK_N 63 10.69322 MIPI_CSI1_LN0_P 66 11.22924 MIPI_CSI1_LN0_N 65 11.33166 MIPI_CSI1_LN1_P 68 11.73285 MIPI_CSI1_LN1_N 67 11.4516 MIPI_CSI1_LN2_P 73 19.19065 MIPI_CSI1_LN2_N 72 19.37532 MIPI_CSI1_LN3_P 71 19.95271 MIPI_CSI1_LN3_N 70 19.87296 Length Difference (DP-DM) mm 0.04892 -0.10242 0.28125 -0.18467 0.07975 3.
3.19 Audio 3.19.1 Audio Interface Pin Definition SU806 series module supports analog audio, have 3 input and 3 output.
5) Reduce noise and improve audio quality, the following approaches are recommended. ⚫ Keep audio PCB routing away from the antenna and high-frequency digital signal. ⚫ Reserve LC filter circuit in audio circuit to reduce EMI. ⚫ Audio routing needs to be masked. 3.19.2 Microphone Circuit Design Module 100pF MIC_P 33pF 33pF MIC_M Figure 3-20 Microphone reference design 3.19.
3.19.4 Headset Circuit Design Module 33 pF MIC2_P HPH_L HPH_R 1K HPH_DET 0R 33 pF 33 pF HPH_GND Figure 3-22 Headset reference design Note: Please choose bidirectional TVS for headset ESD protection. 3.19.5 Speaker Circuit Design Module SPK_P 39pF 39pF SPK_M Figure 3-23 Speaker reference design Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
3.20 Force Download Interface SU806 series module provides KEY_FORCE_BOOT pin as an emergency download interface. Connect the KEY_FORCE_BOOT with GND when power on, the module can enter the emergency download mode which is used for the final processing mode when the product fails to power on or run normally. To facilitate the subsequent software upgrade and product debugging, please reserve the test pin of this pin.
4 Antenna Interface SU806 series module support 2/3/4G main antenna/diversity reception antenna, WIFI/BT antenna and GNSS antenna. 4.1 MAIN/DRX Antenna SU806 series module provides two 2G/3G/4G antenna interfaces. The ANT_MIAN is used to receive and transmit RF signal, the ANT_DRX is used for diversity reception. Table 4-1 Main/DRX pin definition Pin Name Pin Number I/O Description Note ANT_MAIN 87 AI/AO 2G/3G/4G main antenna - ANT_DRX 131 AI Diversity reception antenna - 4.1.
Mode Band Tx (MHz) Rx (MHz) Band 5 824-849 869-894 Band 7 2500-2570 2620-2690 Band 12 699-716 729-746 Band 17 704-716 734-746 Band 28 703-748 758-803 Band 40 2300-2400 2300-2400 Band 41 2496-2690 2496-2690 LTE TDD 4.1.2 Antenna Reference Design When use the SU806 series module, it is necessary to connect the antenna pin with the RF connector or antenna feed point on the main board via an RF trace. Microstrip trace is recommended for RF trace, with insertion loss within 0.
4.2 WIFI/BT Antenna Microstrip trace is recommended for the WIFI/BT RF route, with insertion loss within 0.2dB and impedance at 50Ω. Table 4-5 WIFI/BT antenna interface definition Pin Name Pin Number I/O Description Note ANT_WIFI/BT 77 AI/AO WIFI/BT antenna - 4.2.1 WIFI/BT Operating Frequency Table 4-6 WIFI/BT operating frequency Mode Frequency Unit WIFI 2402-2482 MHz BT4.2 2402-2480 MHz 4.2.
Pin Name Pin Number I/O Description Note ANT_GNSS 121 AI GNSS antenna - 4.3.1 Operating Frequency Table 4-8 GNSS operating frequency Mode Frequency Unit GPS 1575.42±1.023 MHz BeiDou 1561.098±2.046 MHz 4.3.2 GNSS Antenna Reference Design 4.3.2.1 Passive Antenna Reference Design: SU806 series module have a built-in LNA. The passive antenna is used in the design of the device. Microstrip trace is recommended for the GNSS RF route, with insertion loss within 0.2dB and impedance at 50Ω.
4.3.2.2 Active Antenna Reference Design The power of the active antenna is fed from the antenna's signal line through a 56nH inductor. Common active antennas supply power from 3.3V to 5.0V. The active antenna itself consumes very little power, but requires a stable and clean power supply. It is recommended that a high-performance LDO be used to power the antenna. The active antenna reference circuit is shown in the following figure: VDD_3.
SU806 Series Module Antenna Requirement Standard Antenna Requirement Insertion loss: < 2dB (2.3-2.7GHz) VSWR: ≤ 2 Gain (dBi): 1 Max input power (W): 5 WIFI/BT Input impedance (Ω): 50 Polarization type: vertical direction Insertion loss: < 1dB Frequency range: 1559MHz~1607MHz Polarization type: right-circular or linear polarization VSWR: < 2 (typical) GNSS Passive antenna gain: > 0dBi Active antenna NF: < 15dB (typical) Active antenna gain: > -2dBi Reproduction forbidden without Fibocom Wireless Inc.
5 RF PCB Layout Design Guide For user PCB, the characteristic impedance of all RF signal traces should be within 50Ω. In general, the impedance of the RF signal trace is determined by the dielectric constant of the material, the trace width (W), the ground clearance (S) and the height of the reference ground plane (H). The control of the characteristic impedance of the PCB usually in two ways: microstrip trace and coplanar waveguide.
Figure 5-3 Four-layer PCB coplanar waveguide structure (reference ground layer3) Figure 5-4 Four-layer PCB coplanar waveguide structure (reference ground layer4) In the design of RF antenna interface circuit, in order to ensure good performance and reliability of the RF signal, it is recommended to observe the following principles: ➢ The impedance simulation tool should be used to accurately control the RF signal cable at 50Ω impedance.
6 WIFI and Bluetooth 6.1 WIFI Overview SU806 series module supports 2.4G WLAN wireless communications and 802.11b, 802.11g, 802.11n standards, with a maximum speed up to 72.2Mbps. Its characteristics are as follows: ➢ Support Wake-on-WLAN (WoWLAN) ➢ Support ad hoc mode ➢ Support WAPI ➢ Support AP mode ➢ Support Wi-Fi Direct ➢ Support MCS 0-7 for HT20 6.2 WIFI Performance Test condition: 3.
Frequency Mode Date Rate Bandwidth (MHz) Sensitivity (dBm) MCS0 20 -85 MCS7 20 -70 802.11n 6.3 Bluetooth Overview SU806 series module supports BT4.2 (BR/EDR+BLE) standards. The modulation method supports GFSK, 8-DPSK and π/4-DQPSK.BR/EDR. Channel bandwidth is 1MHz and can accommodate 79 channels. The BLE channel bandwidth is 2MHz and can accommodate 40 channels. Its main features are as follows: ➢ BT 4.
7 GNSS 7.1 Overview SU806 series smart module supports GPS/BeiDou positioning systems. The module is embedded with LNA which can effectively improve the sensitivity of GNSS. 7.2 Performance Test condition: 3.8V power supply, environment temperature 25°C Table 7-1 GNSS positioning performance Parameter Description Typical Result Unit Acquisition -146 dBm Tracking -155 dBm -130dBm 39.
8 Electrical, Reliability and RF Performance 8.1 Recommended Parameters Table 8-1 Recommended parameters Parameter Min Normal Max Unit VBAT 3.5 3.8 4.2 V USB_VBUS 4.75 5 5.25 V VRTC - 3.0 3.35 V Operating Temperature -20 25 65 ℃ Storage Temperature -40 25 95 ℃ 8.2 Absolute Maximum Ratings The functionality of SU806 series module is subject to the absolute maximum/minimum values listed in the following table. Do not exceed these parameters or the part may be damaged permanently.
Typical Parameter Description Condition Unit Result Software power off current Isleep By AT command or select the power off menu in LCM selection box 230 GSM MFRMS=5 3.3 WCDMA DRX=8 3.4 TDD LTE DPC (Default Paging Cycle)=#256 3.2 FDD LTE DPC (Default Paging Cycle)=#256 3.2 Radio Off AT+CFUN=4 Flight Mode 2.
Typical Parameter Description Condition Unit Result EGPRS data DCS1800@ Gamma=3(1UL/4DL) 186 DCS1800@ Gamma=3(4UL/1DL) 315 PCS1900@ Gamma=3(1UL/4DL) 183 PCS1900@ Gamma=3(4UL/1DL) 298 GSM850@ Gamma=6(1UL/4DL) 178 GSM850@ Gamma=6(4UL/1DL) 312 EGSM900@ Gamma=6(1UL/4DL) 173 EGSM900@ Gamma=6(4UL/1DL) 315 IEGPRS-RMS mA RMS Current WCDMA IWCDMA-RMS 162 DCS1800@ Gamma=5(4UL/1DL) 318 PCS1900@ Gamma=5(1UL/4DL) 161 PCS1900@ Gamma=5(4UL/1DL) 311 Band2@ max power 588 Band4@ max power 65
Typical Parameter Description Condition Unit Result Band17@ max power(10MHz,1RB) 670 Band28@ max power(10MHz,1RB) 689 TDD data Band40@ max power(10MHz,1RB) 319 RMS Current Band41@ max power(10MHz,1RB) 357 8.4 RF Transmit Power The transmit power of each band of the SU806 module is shown in the following table: Test condition: 3.8V power supply, environment temperature 25°C, maximum power test of LTE 10M 12RB.
Mode Band Max Power (dBm) Min Power (dBm) Band 4 23.0±2 < -39 Band 5 23.0±2 < -39 Band 7 23.0±2 < -39 Band 12 23.0±2 < -39 Band 17 23.0±2 < -39 Band 28 23.0±2 < -39 Band 40 23.0±2 < -39 Band 41 23.0±2 < -39 LTE TDD 8.5 RF Receiver Sensitivity The sensitivity of each frequency band of the SU806 series module is shown in the following table: Test condition: 3.8V power supply, environment temperature 25°C.
Band 5 -99 - - -94.3 dBm Band 7 -98 - - -94.3 dBm Band 12 -98.5 - - -93.3 dBm Band 17 -98.5 - - -93.3 dBm Band 28 -99 - - -94.8 dBm Band 40 -97.1 - - -96.3 dBm Band 41 -97 - - -94.3 dBm LTE TDD 8.6 Electrostatic Protection In the application of the module, due to static electricity generated by human body and charged friction between micro-electronics, etc.
9 Structural Specification 9.1 Product Appearance SU806 series module product appearance is shown in the following figure: Figure 9-1 Module product appearance 9.2 Structural Dimension The structural dimension of SU806 series module is shown in the following figure: Figure 9-2 Structural dimension Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
9.3 PCB Soldering Pad and Stencil Design PCB soldering pad and stencil design please refer to FIBOCOM Sx806 Series SMT Design Guide. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
10 Production and Storage 10.1 SMT SMT production process parameters and related requirements please refer to FIBOCOM Sx806 Series SMT Design Guide. 10.2 Carrier and Storage Carrier and storage please refer to FIBOCOM Sx806 Series SMT Design Guide. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
Appendix A Terms and Acronyms Table A-0-1 Terms and acronyms Term Definition AMR Adaptive Multi-rate bps Bits Per Second CS Coding Scheme DRX Discontinuous Reception EGSM Extended GSM900 Band FDD Frequency Division Duplexing GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSDPA High Speed Down Link Packet Access IMEI International Mobile Equipment Identity Imax Maximum Load Current LED Light Emitting Diode LSB Least Significant Bit LTE Long Term Ev
Term Definition PCB Printed Circuit Board PDU Protocol Data Unit PSK Phase Shift Keying QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly PolarizedRMS RMS Root Mean Square RTC Real Time Clock Rx Receive SMS Short Message Service TDMA Time Division Multiple Access TE Terminal Equipment TX Transmitting Direction TDD Time Division Duplexing UART Universal Asynchronous Receiver & Transmitter UMTS Universal Mobi
Term Definition VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standi
Appendix B GPRS Encoding Scheme Table B-0-1 GPRS encoding scheme Encoding method CS-1 CS-2 CS-3 CS-4 Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.4 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
Appendix C GPRS Multislot In the GPRS standard, 29 types of GPRS multislot modes are defined and can be used by mobile stations. The multislot class defines the maximum rate of uplink and downlink. The expression is 3+1 or 2+2, the first number represents the number of downlink timeslots and the second number represents the number of uplink timeslots. Active timeslot represents the total number of timeslots that the GPRS device can use for both uplink and downlink communications.
Appendix D EDGE Modulation and Encoding Method Table D-0-1 EDGE modulation and encoding method Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1 GMSK - 9.05kbps 18.1kbps 36.2kbps CS-2 GMSK - 13.4kbps 26.8kbps 53.6kbps CS-3 GMSK - 15.6kbps 31.2kbps 62.4kbps CS-4 GMSK - 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.6kbps 35.2kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.8kbps 29.6kbps 59.2kbps MCS-4 GMSK C 17.