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Hardware Functional Overview

FIC MD02 Service Manual 4-1

Chapter

4.1 Overview

The FIC MD02 notebook consists of several important functions and subsystems including:

Notebook size, 2 spindle, IBM PC/AT compatible personal computer with PCI-

bus and Multimedia functions , provide full basic function with lowest price and

easy of use

The following is a summary of MD02 features:

CPU

CPU Type uFCPGA 479pin

Intel Dothan 1.8 GHZ

TDP(Target) 24.5W

Chip Set

Core Logic Intel Montara-GM+ (North) :CPU(Banias) I/F, LVDS I/F,

RGB analog I/F 200/266 DDR MEMORY I/F, Hub-Link I/F,

DVOB&DVOC IF….

Intel ICH4-M (South) : PCI I/F, LPC I/F, ATA100 IDE I/F,

Hub-Link I/F ,AC97 V2.2 I/F, RTC, 2.0/1.1USB I/F,

10/100M LAN I/F, GPIO, ACPI, APIC….

Memory

Support Memory DDR333/266/200 SDRAM 128/256/512MB/1G SO-DIMM

Memory Slots 2 Slots SO-DIMM (1.25”)

Max Memory 2GB (1GB per DIMM )

Video

Controller Embedded in Intel Montara-GM+.

UMA (using DVMT configuration)

High performance & High quality 3D accelerator

High performance 2D accelerator

Complete TV-OUT/Digital flat panel solution

MPEG-2/1 video decoder

Video accelerator

LCD Panel

14.1” XGA

14.1”SVGA+

Controlled by hot key (8 level)

PCMCIA

Controller TI PCI4510 Single Slot PCI-CARDBUS BRIDGE

Built in Smart Card reader(None)

ZV-Port Support (None)

Ring wakeup support(None)

Power Switch TPS2211A(TI)

Sound

Controller

Integrated in Intel ICH4-M (PCI audio)

CODEC Realtek ALC202 AC97 CODEC 2.2 S/PDIF

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Summary of content (20 pages)

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Chapter Hardware Functional Overview 4.1 Overview The FIC MD02 notebook consists of several important functions and subsystems including: Notebook size, 2 spindle, IBM PC/AT compatible personal computer with PCIbus and Multimedia functions , provide full basic function with lowest price and easy of use. The following is a summary of MD02 features: CPU CPU Type TDP(Target) Chip Set Core Logic uFCPGA 479pin Intel Dothan 1.8 GHZ 24.
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Hardware Functional Overview Function Buzzer Volume IEEE 1394(Option) Controller Function Sound Blaster Compatible S/W Wave Table Support (None) SW control. Support one port TI PCI45101 two IEEE1394 ports BRIDGE Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.0 Compliant with Physical Layer Services as defined in P1394a draft 2.0(Data Rate 100/200/400 Mbps) Storage USB FDD IDE bus 3.
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Hardware Functional Overview Modem LAN Docking IR Versa Bay III Keyboard Pitch/Travel Language RJ11 x1 RJ45 x1 Not support Not support Not support 19mm/3mm US, Japan, French, UK, Italian, Spanish, Germany, Belgian Norwegian, Danish, Swedish, Portuguese, T.
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Hardware Functional Overview PC2001 compliant ACPI compliant Plug and Play Support Auto Configuration 16bit I/O Address Decoded Selectable I/O Address, IRQ and DMA 4.2 4-4 System Hardware Block Diagram FIC MD02 Service Manual PDF created with FinePrint pdfFactory trial version http://www.fineprint.
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Hardware Functional Overview Figure 1-1 MD02 Block Diagram 4.
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Hardware Functional Overview Temperature Sensor IEE 1394 NS TI MAX6690 PCI4510 LAN Intel ICH4-M+BroadCom BCM4401 Modem Intel MDC AC’97 4.4 System Processor (CPU) The FIC MD02 runs on Intel Dothan based on uFCPGA packaging. It supports CPU with 1.8 GHZ clock speed rating. The processor operates in conjunction with the RAM and ROM memory and the system control logic to process software instructions (BIOS, Windows, and Applications).
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Hardware Functional Overview dynamic switching between multiple voltage and frequency points instead of two points supported on previous versions of Intel SpeedStep technology. This results in optimal performance without compromising low power. The processor features the Auto Halt, StopGrant, Deep Sleep, and Deeper Sleep low power states.
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Hardware Functional Overview Ø . Support for standard definition DVD (i.e. NTSC pixel resolution of 720x480, etc.) quality encoding at low CPU utilization Video Overlay Ø . Single high quality scalable overlay and second Sprite to support second overlay Ø . Multiple overlay functionality provided via arithmetic stretch BLT(Block Transfer) Ø . 5-tap horizontal, 3-tap vertical filtered scaling Ø . Multiple overlay formats Ø . Direct YUV from overlay to TV-out Ø . Independent gamma correction Ø .
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Hardware Functional Overview Ø n Anti-aliased lines n Hardware-based BLT Clipping and Scissoring n 32-bit Alpha Blended cursor n Programmable 64 x 64 3-color Transparent cursor n Color Space Conversion n Three Operand Raster BLTs n 8-bit, 16-bit, and 32-bit color n ROP support n DIB translation and Linear/Tile addressing .
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Hardware Functional Overview Hub Interface to ICH4-M . 266 -MB/s point-to-point Hub Interface to ICH4-M . 66-MHz base clock Power Management Ø . SMRAM space remapping to A0000h (128-kB) Ø . Supports extended SMRAM space above 256-MB, additional 1-MB TSEG from top of memory, cacheable (cacheability controlled by CPU) Ø . APM Rev 1.2 compliant power management Ø . Supports Suspend to System Memory (S3), Suspend to Disk (S4) and Soft Off (S5) Ø . ACPI 1.0b, 2.0 support Ø .
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Hardware Functional Overview PCI Interface The ICH4 PCI interface provides a 33-MHz, Rev. 2.2 compliant implementation. All PCI signals are 5-V tolerant, except PME#. The ICH4 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH4 requests. IDE Interface (Bus Master Capability and Synchronous DMA Mode) The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and ATAPI devices.
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Hardware Functional Overview incorporates the functionality of two 82C59 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the ICH4 supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform.
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Hardware Functional Overview The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. 4.6 Clock Frequency Generator The notebook utilizes the IMI CY28346 chip to supply the system clock needed to run the computer. The following are the available clock frequencies: System clock: Clock generator IMI CY28346 support: - 66/100 MHz for Pentium III Mobile CPU - 30/33 MHz for PCI device bus clock use - 48 MHz for PIIX4M - 14.
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Hardware Functional Overview The BIOS is stored in a 32-pin PLCC package FLASH ROM SST 49LF040A with 4Mbit size and is mounted into the motherboard. While posting the system, the Shadow RAM will be enabled and the ROM will be disabled. 4.10 Video Subsystem The video subsystem, embedded inside the North Bridge chip and the LCD panel, controls the display output to both the LCD Panel screen and to the external VGA port. 4.10.
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Hardware Functional Overview . Tri-view support through LFP interface, DVO C port, and CRT Internal Graphics Features . Up to 64 MB of Dynamic Video Memory Allocation . Display Image Rotation . Core Frequency • Display Core frequency of 133-MHz • Render Core frequency of 133-MHz .
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Hardware Functional Overview • Color Specular Lighting • Z Bias support • Dithering • Line and Full-Scene Anti-Aliasing • 16 and 24-bit Z Buffering • 16 and 24-bit W Buffering • 8-bit Stencil Buffering • Double and Triple Render Buffer support • 16 and 32-bit color • Destination Alpha • Vertex Cache • Maximum 3D resolution of 1600x1200 at 85- Hz (contact your Intel Field Representative for detailed display information, i.e. pixel depths, etc.
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Hardware Functional Overview with auto configuration capabilities. The PCI4510 is fully complains with the 33Mhz PCI Bus specification, v2.2. It supports a master device with internal CardBus direct data transfer. The PCI4510 implements FIFO data buffer architecture between the PCI bus and CardBus socket interface to enhance data transfers to CardBus Devices. The bi-directional FIFO buffer permits the PCI4510 to accept data from a target bus (PCI or CardBus interface) while simultaneously transferring data.
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Hardware Functional Overview VS# resensing; dedicated ZV output port to LCD controller SmartCardBus™ combines a Smart Card reader and CardBus controller in a single IC. In addition to meeting PC Card standards, SmartCardBus is compliant to Microsoft PC/SC, ISO 7816-1, -2, -3 electrical specifications, standard protocols including T = 0, T = 1, and synchronous and asynchronous formats. SmartCardBus lowers the cost of ownership of ecommerce and corporate security Smart Card applications. 4.
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Hardware Functional Overview module connector includes the PS/2 signal pins, power supply pins and two connections for external button switches. The Synaptic touch pad includes a special “edge-motion” feature that allows the user to extend a drag operation when the finger reaches the edge of the sensor pad. The cursor continues to coast in the indicated direction when the finger is held against the edge. 4.
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Hardware Functional Overview 4.15.4 LCD Inverter Board Assembly The LCD Inverter Board Assembly is located in the LCD Panel Assembly. It converts the +12VDC input directly from the Battery Pack into a high voltage AC output used to light the CCFT (Cold-Cathode Fluorescent Tube). 4.16 Micro-P Subsystem (PMU-08) The micro controller NEC PMU08 acts as a supplement for the power management control. It supports many functions via the SMBus interface.