User's Manual

FLC-BTM805 Datasheet
Flaircomm Microelectronics Confidential
-20-
Symbol
Parameter
Min
Typical
Max
Unit
f
mclk
PCL_CLK
Frequency
4MHz DDS generation.
Selection of frequency
is programmable.
-
128
-
kHz
256
512
48MHz DDS
generation. Selection of
frequency is
programmable.
2.9
-
kHz
-
PCM_SYNC frequency for SCO
connection
-
8
kHz
t
mclkh
(a)
PCM_CLK
high
4MHz DDS generation
980
-
-
ns
t
mclkl
(a)
PCM_CLK low
4MHz DDS generation
730
-
ns
-
PCM_CLK
jitter
48MHz DDS
generation
21
ns pk-pk
Table 6: PCM Master Timing
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Symbol
Parameter
Min
Typical
Max
Unit
t
dmclksynch
Delay time from
PCM_CLK high
to PCM_SYNC
high
4MHz DDS generation
-
-
20
ns
48MHs DDS generation
-
-
40.83
ns
t
dmclkpout
Delay time from PCM_CLK high to valid
PCM_OUT
-
-
20
ns
t
dmclklsyncl
Delay time from
PCM_CLK low to
PCM_SYNC low
(Long Frame Sync
only)
4MHz DDS generation
-
-
20
ns
48MHz DDS
generation
-
-
40.83
ns
t
dmclkhsyncl
Delay time from
PCM_CLK high
to PCM_SYNC
low
4MHz DDS generation
-
-
20
ns
48MHz DDS
generation
-
-
40.83
ns
t
dmclklpoutz
Delay time from PCM_CLK low to
PCM_OUT high impedance
-
-
20
ns
t
dmclkhpoutz
Delay time from PCM_CLK high to
PCM_OUT high impedance
-
-
20
ns
t
supinclkl
Set-up time for PCM_IN valid to PCM_CLK
low
20
-
-
ns
t
hpinclkl
Hold time for PCM_CLK low to PCM_IN
invalid
0
-
-
ns
Table 7: PCM Master Mode Timing Parameters