User's Manual

FLC-WFM301 Datasheet
Flaircomm Microelectronics Confidential
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SD_DATA[0]
DATA: Data line
DAT[0]: Data line 0
DO: Data output
MISO: Data output
SD_DATA[1]
IPQ#: Interrupt
DAT[1]: Data line 1
IRQ#: Interrupt
IRQ#: Interrupt
SD_DATA[2]
RW: Read wait
DAT[2]: Date line 2
Not used
Not used
SD_DATA[3]
CD: Card detect
DAT[3]: Date line 3
CS#: Card select
CS#: Card select
Table 5: Analog IO Usage
All four modes provide identical access to on-chip registers and support clock speeds of up to
50MHz for a maximum burst rate of 200Mbits/s (in SD 4-bit mode). At power-on the host interface
starts in SD 1-bit mode and may be switched into any of the alternative modes via SDIO commands.
4.6.1 SDIO
SDIO mode fully support SDIO specification version 2.00. It supports all defined slave modes (SD 1
bit, SD 4-bit and SDIO SPI), but not SD host functionality.
Two functions are supported:
 Function 0 is the mandatory function used for card configuration. This includes the CCCR, FBR and CIS. Vender-
defined registers within the CCCR support sleep and wake-up signaling.
 Function 1 provides access to the IEEE 802.11 functionality. IO_RW_DIRECT (CMD52) reads and writes on-chip
registers and memory locations directly. IO_RW_EXTENDED (CMD53) transfers blocks of data to or from the
on-chip MMU buffers.
The SDIO interface implements a subset of optional features. Specifically it supports:
 Continuous SPI interrupt (SCSI)
 Direct Commands during data transfer (SDC)
 Multi-block (SMB)
 Read wait (SRW)
4.6.1.1 SDIO Sleep Signaling
WFM301CL supports a variety of mechanisms to enable both itself and the host to efficiently enter
and leave low-power modes.
4.6.1.1.1 Card Sleep and Wake-up
WFM301CL automatically uses its sleep modes to minimize power consumption. Registers in
function 0 are always directly accessible by the host, irrespective of the device’s sleep modes.
Attempts to access function 1 while the device is in deep sleep are likely to results in SDIO timeouts.
To avoid the need for the host to implement complicated retry mechanisms, a simple deep sleep
control scheme is supported via a Vender Unique Register within the CCCR in function 0. The host
uses this register to tell WFM301CL when it is allowed to use deep sleep. When the host
subsequently needs to access function 1 it uses the same register to initiated a wake-up and them
waits for an SDIO interrupt to indicate that the wake-up is compete.