User's Manual
Circuit Diagrams
9.2 Schematic Diagrams
9
9-9
1
ICAL
[1,F10]
GENOUT
[1,A2]
A
B
SENSE
[1,E10]
TRIG_A
[1,E10]
TRIG_B
[2,E10]
C
D
E+5VA
[5,B16]
+3V3A
[5,C16]
F
G
-3V3A
[5,C16]
H
10u100n
C392C391
0E
R395
0E
R385
0E
R375
C7V5
BYD17
BZD27
V360
V354
OPTION
C7V5
BZD27
V353
BC868BC868
V359
V358
261E261E
R356R354
2 3
V356
BC858 C
VDDAA
[4,A11]
PROTECTION
5K11
R352
1K
R353
R371
0E
R376
10E
R377
1E
R378
10E
R381
10E
C381
100n
R393
10E
R394
1E
R396
10E
R398
1E
C398
100n
100n100n100n
C394
C396C397
100n100n100n
C377
C378C379
100n
C382
4 5
APWM_BUS
[4,D1]
REFERENCE
GAIN
VCC5REF
[D8]
VCC5DT
[D11]
VCC3ATR
[D11]
VCC3DT
[D11]
VCC3RAMP
[D11]
VCC3REF
[D8]
VCC3CML
[E9]
C376
100n
VEEATR
[C9]
VEEDT
[D11]
VEERAMP
[E11]
VEEREF
[C10] [D8]
VEECML
[E9] 2x
C393
100n
10K
R309
31K634K8
22u
R311R312
C317
TP304
50PPM
21K5
R308
50PPM
21K5
R306
100K10K
R310R302
10u
10K
C314
R303
100n
C301
10K
R305
3K16
R301
TP301
562K
R326
TP321
681K
TRIGLEV1
R321
681K
TRIGLEV2
R322
TP322
6 7
C322
1n5
C321 REFP
1n5
R327
562K
REFN
REFATT
GAINREFN
REFN
REFP
REFADCT
C313
10u
GAINADCT
GAINADCB
GAINPWM
GAINADCT
REFADCT
TP302 REFADCB
REFPWM1
[5,K2]
[4,E14]
REFADCB
C303
100n
GAINADCB
TP303
REFN
C306
100n
GAINREFN
REFP
REFPWM1
C311
100n
GAINPW M
REF_BUS
[4,J1][4,G6]
[4,C7][4,C2]
[2,F3][2,D10]
[1,F4][1,D10]
[C11]
100n
C312
4041
V301 *
[5,J7]
REFP
TP307
10K
R307
[5,J7]
REFPWM2
TP306
[4,I7]
SCLK
[4,I7]
SDAT
TP309
DACTEST
29DACTESTT
REFPWM
55
REFADCB
53
REFADCT
51
GAINPWM
56
GAINADCB
54
GAINADCT
52
GNDREF
57
VEEREF[G5]
58VEEREF
VCC3REF[F5]
60VCC3REF
VCC5REF[E5]
61VCC5REF
REFP
62
REFN
64
GAINREFN
63
GNDDISTR
7
REFATT
8
TP310
215K34K8
R324R323
8 9
TRIG_B
TRIG_A
BTRAP
ICAL
14
6
10
11
15
13
59
3
1
5
2
4
GNDATR
REFOHMIN
TRIGLEV1
TRIGLEV2
TRIGINB
TRIGINA
SENSE
BOOTSTRAP
GENOUT
ICAL
COHM
CGEN
N301
T-ASIC
OQ0257
TRIGINDIG
GQUALIFY
HOLDOFF
VCC3CML
VEECML
GNDCML
VEECML
SMPCLK
GNDCML
GNDDI
SDA T
SCLK
31
30
27
28
42
40
37
41
38
32
39
36
VCC3CML
VEECML
VEECML
[G5]
[G5]
[F5]
22p
C344
44
33
34
35
GNDDO
TRIGDT
RAMPCLK
ALLTRIG
RSTRAMP
45
GNDCML
43
VEERAMP
46
GNDRAMP
47
VCC3RAMP
48
GNDRDAC
49
TRACEROT
50
GNDDT
26
VEEDT
21
VCC3DT
25
VCC5DT
20
ACDCB
23
ACDCA
22
OHMA
24
BIAS
18
VCC3ATR
17
VEEREF
TRIGINEXT
TVOUT
VEEATR
9
16
12
19
TVOUT
VEEREF
TVSYNC
VEEAT R
[G5]
[G5]
TVOUT
47n
BC848C
C395
TP308
464K
R390
22n
C357
FILM
15 or18n
C356
VCC5REF
10
11
SYNC.
RELAY
CONTROL
PULSE
SEPARATOR
VCC3ATR
C399
100n
R391
1K
TVSYN C
R392
4K22
V395
REF_BUS
[G8]
REFPWM1
R369
26K1
VCC3ATR
[F5]
BIAS
OHMA
ACDCA
ACDCB
VCC5DT
[E5]
VCC3DT
[F5]
VEEDT
[G5]
VCC3RAMP
[F5]
VEERAMP
[G5]
R331
10K
C331
C332
4p7
22p
TP331
R333
TP332
10K
C333
1p
TP311
TP336
R337
10K
C337
4p7
R339
10K
C339
1p
TP338
R342
10K
C342
1p
ST8088-2
0
0
-
0
1-12
3
DTRG_BUS
TRIGQUAL
SMPCLK
HOLDOFF
TRACEROTALLTRIG
TRIGDT
RAMPCLK
348E
R271
RSTRAMP
348E
R171
348E
R173
12 13
+5VA
V174
BCV65
-3V3A
+5VA
V171
BCV65
-3V3A
+5VA
V172
BCV65
-3V3A
[1,E10]
[2,E10]
[4,C5]
K271
110
K171
110
K173
16
14
4041
V302 *
V301 OR V302
See Ch.10, Rev. 14
ST8088-2.WMF
Figure 9-3. Circuit Diagram 3, Trigger Circuit