User's Manual

268XA
Service Manual
6-42
Totalizer Input
The Totalizer Debounce circuit in the PLD (U3) allows the micro controller to select
totaling either the input signal or the debounced input signal. The buffered Totalizer Input
signal (TOT_IN) goes into the PLD at U3 Pin 13. U3 Pin 9 is the debounce enable
control signal. It is active high ( HI = Totalizer Debounced, Lo = Totalizer NOT
Debounced). The Totalizer output from the PLD is on U3 Pin 23 and this signal goes to
the micro controller (CIN U4 Pin 2). The PLD receives its clock from the micro
controller on Pin 2. The clock frequency is approximately 8 kHz. The signal debouncer is
set to approximately 1.75 ms meaning a pulse of less then 1.75 ms will not pass through.
In debounce mode, the maximum repetitive frequency of the Totalizer signal is
approximately 500 Hz. In non-debounce mode, the maximum repetitive frequency of the
Totalizer is approximately 5 kHz.
If the pulse duration of the Totalizer is greater then 1.75ms, the Totalizer signal is passed
to the output of the PLD (U3 Pin 23). If the duration of the Totalizer signal is less than
1.75ms, it is removed (debounced). Selection of either “debounced” or “non-debounced”
input is controlled by the DEBOUNCE_EN control signal (U3 Pin 9). Debounce is
selected when DEBOUNCE_EN is high. From the PLD, the signal (TOTAL) is routed to
a 16 bit counter in the micro controller (CIN U4 P2). The Totalizer counter is a 32 bit
counter using a combination of the internal counter and a 16-bit storage register internal
to the micro controller.
Totalizer Enable
Operation of the Totalizer is controlled by the TOT_ENABLE signal. The Totalizer
Enable signal is active high. Applying a logic low to TOT_ENABLE will disable
counting by the Totalizer. TP_ENABLE* is the control signal to the micro controller (U4
Pin 8); Totalizer counting is enabled when this signal is held low.
Digital Output PCA Troubleshooting
The Digital Output Connector PCA has no active components. It consists of the A62 PCB
and screw type terminal blocks. Melted traces from excessive current or contamination
from foreign matter getting between traces are about the only problems that this module
can have. Both problems can be troubleshot with a DMM.
A3 A/D Converter Module Troubleshooting
To access this card for test, the user may need the 2680A-7001K Extender kit, p.n.
1619174. The following paragraphs provide troubleshooting hints for the A3 A/D
Converter PCA. Use this material in conjunction with Chapter 2, “Theory of Operation.”
XWWarning
To avoid electric shock, disconnect all channel inputs from the
device before performing any troubleshooting operations.
A3 Kernel
If the microprocessor detects a fault, it drives the HALT* signal low and in essence halts
itself. Monitor the HALT* line and if it is not steady and toggles between low and high,
then there is most certainly a problem with the A3 kernel. In this instance, check the pull-
up resistors for the data and addressing lines, and then signal conditions at the kernel
devices. Incorrect jumper settings (Table 6-12) can also cause kernel problems.