3161A-SL Wi-Fi Single-band 1X1 802.
3161A-SL Module Datasheet Office: 6 Floor, Building U6, Junxiang U8 Park, Hangcheng Avenue, Bao'an District, Shenzhen City, CHINA Factory: No.8, Litong Road, Liuyang Economic & Technical Development Zone, Changsha, Hunan, CHINA TEL: +86-755-2955-8186 Website: www.fn-link.
161A-SL Revision History Version Date Revision Content Draft Approved 1.0 2020/04/22 New version Lxy Szs 1.
3161A-SL CONTENTS 1 Overview....................................................................................................................................1 1.1 Introduction......................................................................................................................... 1 1.2 Features.............................................................................................................................. 1 1.3 General Specification...........................................
3161A-SL 1 Overview 1.1 Introduction 3161A-SL is a highly integrated 2.4 GHz Wi-Fi module that support the IEEE 802.11b/g/n baseband and RF circuit. It supports 20 MHz standard bandwidth and 5 MHz/10 MHz narrow bandwidth, and provides a physical layer rate up to 72.2 Mbit/s.
3161A-SL Maximum rate of 72.2 Mbit/s@HT20 MCS7 SDIO interface for Wi-Fi Low power dissipation High transmitting power High receiving sensitivity PHY supporting IEEE 802.11b/g/n MAC supporting IEEE802.11 d/e/h/i/k/v/w Module integrated 32K clock WFA WPA, WFA WPA2 personal, and WPS2.0 for Wi-Fi Built-in 352 KB SRAM and 288 KB ROM Main chipset Built-in 32bit MCU and 2 MB flash memory 1.
3161A-SL 2 Wi-Fi RF Specification 2.1 2.4GHz RF Specification Feature Description WLAN Standard IEEE 802.11 b/g/n Wi-Fi compliant Frequency Range 2.400～2.4835GHz Number of Channels Spectrum Mask Wi-Fi: US: channel 1~11; EU: channel 1~13; Japan: channel 1~14; Typ. b/g/n Max. b/g/n Unit b/g/n 1st side lobes(to fc ± 11MHZ) - -43/-30/-40 - dBr 2st side lobes(to fc ± 22MHZ) - -52/-33/-58 - dBr Freq. Tolerance -20/-20/-20 - 20/20/20 ppm Test Items Typical Value EVM 802.
3161A-SL Maximum Input Level Antenna Reference - MCS=5 PER @ -78 dBm ≤-76 dBm - MCS=6 PER @ -76 dBm ≤-74 dBm - MCS=7 PER @ -73 dBm ≤-72 dBm 802.11b: -10 dBm 802.11g/n: -20 dBm PCB antenna with 0~2 dBi peak gain 3 Pin Assignments 3.
3161A-SL 3.2 Pin Definition NO Name Type Description Voltage 1 GND － Ground connections 2 WL_ANT I/O RF I/O port 3 GND － Ground connections 4 NC － Floating (Don’t connected to ground) 5 NC － Floating (Don’t connected to ground) 6 Host wake device I Host Wake up Wi-Fi,GPIO06 VDDIO 7 GPIO8 I/O GPIO or configured as SDIO interrupt pin. (If not used keep Floating) VDDIO 8 NC － Floating (Don’t connected to ground) 9 VCC P Main power voltage source input 2.3V-3.
3161A-SL 33 GND － Ground connections 34 NC - Floating (Don’t connected to ground) 35 NC － Floating (Don’t connected to ground) 36 GND － Ground connections － UART0_LOG_TX,GPIO03 For firmware download, can floating this pin VDDIO UART0_LOG_RX,GPIO04 For firmware download, can floating this pin VDDIO 37 UART_LOG_TX 38 UART_LOG_RX － 39 WL_RST I 40 Dev_Wake_Host O Wi-Fi wake up host.
3161A-SL 19 GPIO14 GPIO14 UART2_CTS UART0_LOG_RX PWM5 I2C0_SCL / SDIO_D1 / Notes： 1. IO 类型：Ispu/O. 2. 驱动电流 1mA. 3. 电压 3.3/1.8V. 4 Dimensions 4.1 Module Picture L x W : 12 x 12 (+0.3/-0.1) mm H: 2.3 (±0.2) mm Weight 0.66g 4.
3161A-SL 4.3 Module Physical Dimensions (Unit: mm) < TOP VIEW > 0,25 1,15 0,65 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 1,15 0,65 0,25 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 4.
3161A-SL < TOP VIEW > 6,25 6 5,125 FN-LINK TECHNOLOGY LIMITED 0,25 1,15 0,65 6,25 6 5,125 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 1,15 0,65 0,25 4,75 4,25 3,85 3,35 2,95 2,45 2,05 1,55 9 Proprietary & Confidential Information
3161A-SL 5 Host Interface Timing Diagram 5.1 SDIO Pin Description The secure digital input/output (SDIO) interface supports three working modes: Default speed mode (DS) The maximum frequency of the interface clock is 25 MHz. The interface clock can work in 1-bit or 4-bit mode. High speed mode (HS) The maximum frequency of the interface clock is 50 MHz.
3161A-SL Figure 8-6 shows the output data timing in DS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode.
3161A-SL Figure 8-7 shows the input data timing in DS mode. Where, tODLY(max) is the maximum delay of the output data relative to the clock falling edge, and tODLY(min) is the minimum delay of the output data relative to the clock falling edge. Table 8-12 describes the timing restrictions in DS mode.
3161A-SL Note: In DS mode, the output data is referenced to the clock falling edge, and the input data is referenced to the clock rising edge. HS Mode The HS mode is entered after the SDIO is powered on and initialized because a higher working rate than the DS mode is required. In HS mode, the clock supports 50 MHz. For details about the restrictions on the clock, see Table 8-13.
3161A-SL Figure 8-8 shows the input data timing in HS mode. tISU is the setup time, that is, the stability time required by the data of the SDIO interface before clock sampling in this mode. tIH is the hold time, that is, the time required by the data of the SDIO interface to retain the original level after clock sampling in this mode Figure 8-9 shows the input data timing in HS mode.
3161A-SL Table 8-15 describes the timing restrictions in HS mode. Table 8-16 Timing restrictions in HS mode (VDDIO = 1.
3161A-SL Note: The data signal timing in HS mode is different from that in DS mode. The output data and input data are referenced to the clock rising edge. SDR25 Mode The SDR25 mode is entered only after the voltage of the SDIO is switched. In this mode, the maximum interface clock frequency is 50 MHz. Table 8-17 describes the clock restrictions.
3161A-SL FN-LINK TECHNOLOGY LIMITED 17 Proprietary & Confidential Information
3161A-SL FN-LINK TECHNOLOGY LIMITED 18 Proprietary & Confidential Information
3161A-SL 6 Reference Design VDDIO VDDIO 6.1 4line SDIO Reference Design R10 NC/4.7K 1 L1 10pF WL_ANT 2 3 C1 NP C2 NP 4 5 HOST WAKE DEV 6 MUTI FUNCTION 7 3.3V 8 9 10 C3 4.7uF 11 34 NC NC UART0_LOG_TX 35 36 37 预留 C10 C11 NC/680pF NC/680pF GND UART_RX UART_TX WL_RST UART0_LOG_RX DEV WAKE HOST 38 39 41 42 43 40 WL_RST DEV2HOST_WAKE NC NC NC NC 44 R11 NC/4.
3161A-SL 6.2 1line SDIO Reference Design 设计注意事项： 1. Hi3861L 与 Hi18EV300 互连的以下管脚请完全拷贝海思设计，禁止修改。 − GPIO8 − GPIO11 − GPIO12 − GPIO13 这些管脚会由软件上的 Hisyslink 组件直接控制，Hi3861L 的 SDIO 使用 1 线模式 配置。 2. 3161A WIFI 上电复位 (POR：Power On Reset)期间，GPIO2/GPIO6/GPIO8 不能 输入高电平，否则芯片可能出现未知异常，如出现 Flash 被写保护等问题。任何在 上电器件可能出现高电平的应用都禁止接入到 GPIO2/GPIO6/GPIO8，如 PIR 输 入、按键输入、USB 插入检测。待 Hi3861L 上电完成 POR 后，这些管脚可以输入 高电平。 3.
3161A-SL 4. 当 WIFI 待机时，外部设备可以通过 GPIO3/GPIO5/GPIO7/GPIO14 以中断方式唤 醒 WIFI。 5. 由于管脚有限，在 GPIO7 上接了三个按键。使用方法为先使用 GPIO 中断，在获 取到 GPIO 中断后，再复用成 ADC 进行电压采集，以区分按键。 6. WIFI IO 电平与 VDDIO 供电电压一致。当 VDDIO 采用 3.3V 供电时，WIFI IO 配置为 3.3V。 门铃button reset按键等 or UART0 34 NC UART0_LOG_TX 36 35 NC GND UART_TX ADC 37 PIR_OUT 39 UART0_LOG_RX UART_RX WL_RST 41 42 43 NC VBAT GPIO01 GPIO14 31 30 29 28 27 26 25 24 23 VDDIO NC 32 22 NC RTC_CLK VDDIO C51 4.
3161A-SL cover Main Crystal Alt. Crystal Main RTC Main Chipset positioning foot (material: copper) Xintai 2520 40MHZ,13.8PF,7ppm,SR:50 Ω ,E2SB40E00000GE (HOSONIC) 2520 40MHz 15pF ±10ppm -40~85℃ Q40000V024 （东 晶） 3215 32.768KHZ 12.5PF SF32K32768D31T-12.5 (泰晶) 20PPM -40~85 ° C Hi3861LRNIV100 WiFi IoT Soc,802.
3161A-SL Number of Times : 2 times 12 Packing Information 12.
3161A-SL 12.2 Carrier Tape Detail 12.
3161A-SL 12.4 Moisture sensitivity The Modules is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions: a) Calculated shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH). b) Environmental condition during the production: 30°C / 60% RH according to IPC/JEDEC J-STD-033A paragraph 5.
