Data Sheet

6223B-U
UD
FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential
Information
11
6 Interface Timing Specification
6.1 Power On Sequence
T
on
: the main power ramp on duration
T
por
: the power on reset releases and power management unit executes power on tasks
T
attach
: USB attach state
T
k-st
ate
: the duration from resister attached to USB host starting card detection procedure
The power on flow description:
After main 3.3V ramp up, the internal power on reset is released by power ready
detection circuit and the power management unit will be enabled. The power
management unit enables the internal regulator and clock circuits.
The power management unit also enables the USB circuits.
USB analog circuits attach resisters to indicate the insertion of the USB device.
The typical timing range:
Unit Min Typical Max
T
on
ms 0.2 1.5 5
T
por
ms -- 2 10
T
xt
al
ms -- 1.5 8
T
at
tach
ms 100 250 --
T
1V25
ms -- 2 5
T
en
ms 0 0 5