欧智通科技 Fn-Link 8110N-UR WiFi Single-band 1X1 Module Datasheet
8110N-UR Revision History Version 1.
1. Introduction 8110N-UR ........................................................................................................... 4 2. Hardware Specification .......................................................................... 6 2.1 8110N-UR module pinout..................................................................................................................................6 2.2 8110N-UR Interface summary .................................................................................
8110N-UR 1. Introduction 8110N-UR Wi-Fi module provides a highly-integrated and flexible platform for developing and evaluating products and applications based on the QCA4010 SoC. 8110N-UR module includes the following components: ■ QCA4010 chip ■ An integrated Balun to save cost and size, minimize tuning and tolerance ■ A printed antenna ■ Apple MFI (optional) ■ 2MB SPI Flash memory and etc. The QCA4010 is a single band 1x1 802.
8110N-UR 8110N-UR Wi-Fi link features ■ IEEE 802.11 b/g/n, single stream 1x1 ■ Single-band 2.4 GHz ■ Integrated PA and LNA; ■ Green Tx power saving mode ■ Low power listen mode ■ Four-layer PCB design ■ Data rates up to 150 Mbps ■ Full security support: WPS,WEP, TKIP,WPA (personal),WPA2 (personal) 8110N-UR manufacturing interface ■ USB 2.
8110N-UR 2. Hardware Specification 2.
8110N-UR Table 2-1 8110N-UR module pinout definition and QCA4010 GPIO assignment Pin Signal/Interface ALT1 ALT2 － 1 GND Ground － 2 WIFI_UART1_RXD High speed UART RXD － 3 WIFI_UART1_TXD High speed UART TXD － 4 WIFI_UART1_RTS High speed UART RTS － 5 WIFI_UART1_CTS High speed UART CTS － 6 PWM7 PWM7 － 7 PWM6 PWM6 I2C Slave 8 PWM5_I2CS_SDA0 PWM5 SDA0 I2C Slave 9 PWM4_I2CS_SCK0 PWM4 SCK0 － 10 PWM0 PWM0 － 11 PWM2 PWM2 － 12 GND Ground 13 SPI_MISO_SDIO_D0_UART2_RTS SPI MISO (master or slave) SDIO Data0 14 SPI_CLK_SD
110N-UR Debug UART TXD － GPIO[29] － GPIO[28] ADC1 Debug UART RXD － － － ADC0 ADC0 － － － 42 GND Ground － － － 43 I2CM_SDA0 I2C Master SDA0 － － GPIO[25] 44 I2CM_SCL0 I2C Master SCL0 － － 45 GND Ground － － GPIO[26] － 46 GND Ground － － － 38 ADC6_UART0_TX ADC6 39 ADC7_UART0_RX ADC7 40 ADC1 41 2.2 8110N-UR Interface summary ■ Host interface: SPI master x 1, SDIO2.
8110N-UR 2.4 Electrical characteristics 2.4.1 Absolute Maximum Ratings Table 2-4-1 summarizes the absolute maximum ratings and Table 2-4-2 lists the recommended operating conditions for the 8110N-UR. Absolute maximum ratings are those values beyond which damage to the device can occur. Functional operation under these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended.
8110N-UR 2.4.3 General DC electrical characteristics These conditions apply to all DC characteristics unless otherwise specified: Tamb = 25 °C, Vin = 3.3 V Table 2-4-3 DC Electrical characteristics for digital I/Os Symbol Parameter Min Typ Max Unit VIH High level I voltage 1.8 － 3.6 V VIL Low level I voltage -0.3 － 0.3 V VOH High level O voltage 2.2 － 3.3 V VOL Low level O voltage 0 － 0.4 V 2.4.
8110N-UR 2.4.5 8110N-UR radio Tx characteristics Table 2-4-5 8110N-UR Tx characteristics for 2.4GHZ operation Symbol Parameter Conditions Min Typ Max Unit Ftx Tx output frequency range － 2.412 － 2.472 GHz 802.11b mask compliant 1 Mbps － 19 － 802.11g mask compliant 6 Mbps － 19 － 802.11g EVM compliant 54 Mbps － 16 － 802.11n HT20 mask compliant MCS0 － 19 － 802.11n HT20 EVM compliant MCS7 － 15 － Output power Pout Refer to IEEE802.
8110N-UR 2.5 Timing specifications 2.5.1 SPI master interface timing Figure 2-3 8110N-UR SPI master timing Table 2-5-1 SPI master timing Parameter Description Min Max Unit tCP Clock period 30.7 1000 ns tCSD Chip select valid delay -5.5 5 ns tDD Data valid delay -5.
8110N-UR 2.5.2 SPI slave interface timing Figure 9-2 SPI Slave Timing Table 2-5-2 SPI slave timing Parameter Description Min Max Unit fPP Clock frequency 0 48 MHz tWL Clock low time 8.3 － ns tWH Clock high time 8.
8110N-UR 3. Mechanical Interface Specification Figure 3-1 8110N-UR module dimensions Table 3-1 8110N-UR module dimensions Label Dimension(mm) A 16 B 30 C 2.285 D 2.54 E 1.27 F 0.4 G 0.7 H(diameter) 0.5 Module height(including the RF shield) 2.6 Total height (with a coax cable plugged into the U.FL connector) 3.
8110N-UR 4. Manufacture information 4.1 Optical Inspection After SMT, 8110N-UR PCBA will be automatically sent to do AOI (Automatic Optic Inspection). Longsys uses TR7500 to check every CHIP. TR7500 features: 3CCD camera with 5 detectors All pictures have the sense of 3D Resolution: 10μm TR7500 can detect blemishes during SMT to guarantee quality at the first step before IOE and fully functional test. 4.
8110N-UR 5.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
