Data Sheet

8110N-UR
FN-LINK TECHNOLOGY LIMITED 11 Proprietary & Confidential Information
2.5 Timing specifications
2.5.1 SPI master interface timing
Figure 2-3 8110N-UR SPI master timing
Table 2-5-1 SPI master timing
Parameter Description Min Max Unit
tCP Clock period 30.7 1000 ns
tCSD Chip select valid delay -5.5 5 ns
tDD Data valid delay -5.5 5 ns
tDS Data setup 3
－
ns
tDH Data hold 0
－
ns