Data Sheet

F89ESSM23
FN-LINK TECHNOLOGY LIMITED
12
Tnon_rdy: SDIO not ready duration. In this state the RTL8189ES may respond to commands without the
ready bit set. After the ready bit is set, the host will initiate the full card detection procedure.
Power-On Flow Description
We recommend that the card detection procedures are divided into two phases: a 3.3V power pre-charge
phase and a formal power-up phase.
For the 3.3V power pre-charge phase, the power ramp up duration is not limited. The 3.3V is then cut off
and is turned on after a Toff period. The ramp up time is specified by the T33ramp duration.
After main 3.3V ramp up and 1.2V ramp up, the power management unit will be enabled by the power
ready detection circuit, and will enable the SDIO block. eFUSE is then autoloaded to the SDIO circuits
during the Tnon_rdy duration. After the autoload has completed, the SDIO sets the ready bit. After CMD5/
5/3/7 procedures, card detection is then executed. After the driver has loaded, normal commands 52 and 53
are then used.
A typical timing specification is shown below:
Parameter
Min
Typical
Max
Unit
T
33ramp’
-
-
No Limit
ms
T
off
250
500
1000
ms
T
33ramp
0.1
0.5
2.5
ms
T
12ramp
0.1
0.5
1.5
ms
T
por
2
2
8
ms
T
non-rdy
1
2
10
ms
7.3.3 GSPI Interface Power-On Sequence
The GSPI interface is enabled automatically when a valid GSPI command is first received. The recommended
power-on sequence is as follows: