Data Sheet

H158A-S
FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information
10
download, including the initial device power-on reset evoked by LDO_EN signal. The
LDO_EN input level must be kept the same as VDDIO voltage level. After initial
power-on, the LDO_EN signal can be held low to turn off the SV615XP or pulsed low to
induce a subsequent reset. After LDO_EN is assert and host starts the power-on
sequence of the SV615XP. From that point, the typical SV615XP power-on sequence is
shown below:
1. Within 1.3 millisecond, the internal power-on reset (POR) will be done. And host could
download firmware code of DPLL setting if the crystal is not default setting, 26MHz. The
internal running clock is crystal frequency.
2. After 100us of DPLL settling time, host could set internal clock to full speed and finish
all the downloading of firmware code.