Data Sheet

H158A-SM
FN-LINK TECHNOLOGY LIMITED Proprietary & Confidential Information
11
DATA3 Data Line 3
CLK Clock
CMD Command Line
6.2 SDIO Default Mode Timing Diagram
6.3 SDIO Power-on sequence
Figure 4 shows the power-on sequence of the SV615XP from power-up to firmware
download, including the initial device power-on reset evoked by LDO_EN signal. The
LDO_EN input level must be kept the same as VDDIO voltage level. After initial
power-on, the LDO_EN signal can be held low to turn off the SV615XP or pulsed low to
induce a subsequent reset. After LDO_EN is assert and host starts the power-on