Assembly Instructions

69

0DLQERDUG
6.1. Mainboard Jumpers
43
4
30
41
54
40
7
)LJXUH 0DLQERDUG-XPSHUV
7DEOHMainboard Jumpers
Header -XPSHU6HWWLQJ 'HIDXOW )XQFWLRQ'HVFULSWLRQ
J54 N/A V UEFI_SEL select signal. Default not assemble
jumper on J54.
JP(1-2) When assemble jumper on J54, force UEFI_SEL to
LOW.
J40 N/A V Reserve main processor RESET_PWRUP_N path
from CPLD. Default not assemble jumper on J40.
JP(1-2) When assemble jumper on J40, main processor
RESET_PWRUP_N source is from CPLD.
J42 JP(1-2) V 0DLQSURFHVVRU63,ÀDVK:3VLJQDO'HIDXOW
assemble JP42 on J42 pin 1-2, normal operation.
JP(2-3) Assemble JP42 on J42 pin 2-3, enable HW WP#.