Specifications

COMPANY CONFIDENTIAL
11
1.4.2 Pin definition
T
able 1-1 M.2 Pin definition.
CONFIG_2 (GND) 75
74 3.3V GND 73
72 3.3V GND 71
70 3.3V CONFIG_1 (GND) 69
68 ANT_CONFIG (I)(0/1.8V) See item
1.5.10
RESET# (I)(0/1.8V) 67
66 SIM DETECT (I) ANTCTL3 (O)(0/1.8V) 65 1. Pin59~65 for external
GPIO antenna tuner
contorl
2. Pin 59 reserve for
PCM interface
(PCM_Out)
3. Pin 61 reserve for
PCM interface
(PCM_CLK)
4. Configure by SW
64 COEX_TXD (O)(0/1.8V) Dual layout
3GPIOs and
UART I/F for
LTE / Wi-Fi
coexistence
ANTCTL2 (O)(0/1.8V) 63
62 COEX_RXD(I)(0/1.8V) ANTCTL1 (O)(0/1.8V) 61
60 COEX3(I/O)(0/1.8V) ANTCTL0 (O)(0/1.8V) 59
58 MIPI_CLK (0/1.8V) For external
tunable
antenna (MIPI)
GND 57
56 MIPI_DATA (0/1.8V) Not connect (Reserve
as REFCLKP)
55 Without PCIe support
54 PEWAKE# (IO)(0/3.3V) Not connect (Reserve
as REFCLKN)
53
52 CLKREQ# (IO)(0/3.3V) GND 51
50 PERST# (I)(0/3.3V) Not connect (Reserve
as PERp0)
49 Without PCIe support
48
UIM_2
PWR (O)
USIM_2 for on
board eSIM
and reserve for
external 2
nd
USIM
Not connect (Reserve
as PERn0)
47
46
UIM_2
RESET (O)
GND 45
44
UIM_2
CLK (O)
Not connect (Reserve
as PETp0)
43 Without PCIe support
42
UIM_2
DATA (IO)
Not connect (Reserve
as PETn0)
41
40 SIM DETECT (2) GND 39
38 Not connect
USB3.0
Rx+
37
36
UIM_1
PWR (O)
USIM_1
connect to
external SIM
socket
USB3.0
Rx
35
34
UIM_1
DATA (IO)
GND 33
32
UIM_1
CLK (O) USB3.0
Tx+
31
30
UIM_1
RESET (O) USB3.0
Tx
29
28
GPIO_8
AUDIO_3 (IO) (0/1.8V)
Reserve PCM
interface
(PCM_Sync)
GND 27
26
GPIO_10
W_DISABLE2# (I) (0/3.3.V)
3.3V I/O DPR (I)(0/1.8V) 25 1.8V I/O
24
GPIO_7
AUDIO_2 (IO) (0/1.8V)
Antenna tuner
power (1.8V)
GPIO_11
WoWWA
N# (O)(0/1.8V)
23
22 ANT_TUNER_CONFIG(I)(0/1.8V) Antenna tuner
mode control
CONFIG_0 (GND) 21
20
GPIO_5
AUDIO_0 (IO)(0/2.7V)
Antenna tuner
power (2.7V)
Module Key 13~19
12~18
Module Key GND 11
10
GPIO_9
LED#1 (O)(Open drain)
USB_D
9
8 W_DISABLE1# (I)(0/3.3V) 3.3V I/O USB_D+ 7
6 FULL_CARD_POWER_OFF# (I)(0/3.3V)
3.3V I/O GND 5
4 3.3V GND 3
2 3.3V CONFIG_3 (N/C) 1
Notes: Foxconn will provide one excel file to explain the PCIe M.2 Pin connection after
project award.