User's Manual

System Overview and Functional Block Descriptions
1322x Network Node Reference Manual, Rev. 1.1
Freescale Semiconductor 3-5
3.7 128x64 Pixel Monochrome Graphic LCD Display
The Network Node supports a 128x64 pixel chip-on-glass (COG) STN transmissive monochrome graphic
LCD that provides for alpha-numeric or graphic readout. The LCD module is mounted on top of the main
circuit board and connects via a flat flex cable (FFC).
• The display is an OPTREX #F-51553GNBJ-LW-AB
• Viewing area is 66.8 (W) × 35.5 (H) mm
• The LCD operates from 5 Vdc generated from the main operating voltage. The LCD module
requires a highly regulated 5 V so that the high voltages generated onboard the display are
consistent.
• The LCD has white LED backlighting with a typical current of 40 mA when full on. The
backlighting is switched by a FET and can be modulated to save current and vary the intensity.
• LCD interface to the MCU is via an 8-bit parallel interface
• The onboard controller is a member of the Epson S1D15605 Series family with an integrated
display data RAM
3.8 Debug/Development Interfaces
There are two separate debug ports (for pinouts see Section 4.7, “Debug/Development Connectors”). A
20-pin connector is provided for a standard JTAG debug interface. This a lower cost option that only
requires a simple interface cable to connect to the PC and use standard ARM software development tools.
A separate 38-pin Mictor connector is uniquely provided on this module to support the extended capability
Nexus real-time debug interface for the ARM processor.
3.9 Audio Subsystem
The audio subsystem provides means for simple output sounds/tones or for TELCO voice quality audio.
• A 2.5mm stereo jack is provided to interface to a typical telephone-type headset with an electret
microphone and a single earphone.
• Audio input - The audio input is taken from the headset electret microphone (mic).
— An onboard 10 k-ohm resistor circuit biases the mic for an ~1 Vdc operating voltage.
— The mic AC signal is filtered and amplified through a active low-pass filter with a voltage gain
of about 30 (~30 dB). The filter topology is a multiple feedback (MFB) 3-pole, linear phase
design. The target cutoff frequency is 3.6 kHz. The filter is intended as an anti-aliasing filter
for sampled data.
— The input amplifier output is sampled via the onboard MC1322x ADC. The sampling
frequency is programmable.
• Audio output source - The audio output can be sourced from both a serial 10-bit DAC and a PWM
timer output.
— The 10-bit serial DAC uses the SSI port to send provide the digital sample data.
— The PWM timer output is typically modulated to create a Class-D amplifier. Secondarily, a
simple 50% duty cycle signal can provide simple tones.